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參數(shù)資料
| 型號： | SAA7201 |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| 中文描述： | 集成MPEG2解碼器的AVG（綜合的MPEG音頻視頻圖表譯碼器） |
| 文件頁數(shù)： | 13/36頁 |
| 文件大?。?/td> | 292K |
| 代理商： | SAA7201 |
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1997 Jan 29
13
Philips Semiconductors
Objective specification
Integrated MPEG2 AVG decoder
SAA7201
System time base unit
The system time base unit serves as a timing master for all
internal processes. It consists of two 24-bit wide System
Time Clock (STC) counters, running at 90 kHz. The STCs
will be used as internal synchronization reference for audio
and video.The contents of the STC can be loaded by the
external CPU which should insure that the phase of the
SAA7201 internal STC is identical to the main system time
clock in the system demultiplexer. The CPU should correct
for possible latency problems.
Because two counters are implemented, the previous time
base reference which might still be required as reference
for some time in case of time base discontinuity, can be
maintained. Thus all information for audio/video
synchronization is available in the decoder chip and only
minor support of the external controller is required.
The synchronization of graphics for e.g. subtitling, should
be controlled by the external CPU.
Video input buffer and synchronization control
The size and position of the video input buffer in the
external SDRAM is programmable. By default 2.6 Mbit/s
are reserved for the video input buffer but in principle any
other value can be programmed. The current fullness of
the video input buffer can be monitored by the CPU and an
internal interrupt will be generated is case of either near
over- or near underflow.
Data retrieval from the input buffer can be controlled by
DTS time stamps parsed from the PES or MPEG1 packet
stream. For those frames where no DTS time stamp is
present in the video bitstream a DTS is emulated by the
SAA7201.
Obviously this emulation mode can also be used when the
input stream is a video elementary stream (ES). The latter
case should be handled by start and stop decode
commands from the CPU.
The external CPU can select to retrieve the video PES
header and/or video PES private data for further software
processing.
Audio input buffer and synchronization control
The audio input buffer and synchronization control
basically behaves identical to its video counter part.
The default buffer size is 64 kbit in this case.
Synchronization will be controlled by PTS time stamps in
the audio Packetized Elementary Stream. Also in this case
an PTS emulation or a free running start/stop controlled
mode are supported.
Audio decoder
A functional block diagram for the audio decoding part is
depicted in Fig.5.
Fig.5 Audio decoding unit.
handbook, full pagewidth
BUFFER AND
SYNC UNIT
AUDIO
CLOCK
GENERATOR
AUDIO
BEEP
DRAM-bus
81 MHz
MPEG
AUDIO
DECODER
OUTPUT
INTERFACE
Sony or
I
2
S-bus
SPDIF
MGD325
Audio decoding unit
+
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|---|---|
| SAA7201H | Integrated MPEG2 AVG decoder |
| SAA7212 | Integrated MPEG2 AVG Decoder(綜合MPEG音頻視頻圖表譯碼器) |
| SAA7212H | Integrated MPEG AVG decoder |
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| SAA7201H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Integrated MPEG2 AVG decoder |
| SAA7205 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer |
| SAA7205H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:MPEG-2 systems demultiplexer |
| SAA7206 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
| SAA7206H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:DVB compliant descrambler |
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