I
參數(shù)資料
型號: SAA7706H/N107S,518
廠商: NXP Semiconductors
文件頁數(shù): 27/52頁
文件大?。?/td> 0K
描述: IC DSP CAR RADIO 80QFP
標(biāo)準(zhǔn)包裝: 500
類型: 汽車信號處理器
接口: I²C,I²:S,LSB,SPDIF
電壓 - 輸入/輸出: 3.30V
電壓 - 核心: 3.30V
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 80-BQFP
供應(yīng)商設(shè)備封裝: 80-QFP(14x20)
包裝: 帶卷 (TR)
2001 Mar 05
33
Philips Semiconductors
Product specication
Car radio Digital Signal Processor (DSP)
SAA7706H
9.6
I2C-bus memory map specication
The I2C-bus memory map contains all defined I2C-bus bits. The map is split up in two different sections, the hardware
memory registers and the RAM definitions. In Table 5 the preliminary memory map is depicted. The hardware registers
are memory map on the XRAM of DSP2. Table 5 shows the detailed memory map of those locations. All locations are
acknowledged by the SAA7706H even if the user tries to write to a reserved space. The data in these sections will be
lost. Reading from this locations will result in undefined data words.
Table 4
I2C-bus memory map
Table 5
I2C-bus memory map overview of hardware registers
ADDRESS
FUNCTION
SIZE
2000H to 21FFH
YRAM (DSP2)
512
× 12 bits
1FF0H to 1FFFH
hardware registers
16
× 24 bits
1000H to 127FH
XRAM (DSP2)
640
× 24 bits
0FFFH
DSP CONTROL
1
× 16 bits
0800H to 097FH
YRAM (DSP1)
384
× 12 bits
0000H to 017FH
XRAM (DSP1)
384
× 18 bits
DESCRIPTION
REGISTER
Hardware registers
Program counter register DSP2
1FFFH
Status register DSP2
1FFEH
I/O conguration register DSP2
1FFDH
Phone, navigation and audio register
1FFCH
FM and RDS sensitivity register
1FFBH
Clock coefcient register
1FFAH
Clock settings register
1FF9H
IAC settings register
1FF8H
Selector register
1FF7H
CL_GEN register 4
1FF6H
CL_GEN register 3
1FF5H
CL_GEN register 2
1FF4H
CL_GEN register 1
1FF3H
Evaluation register
1FF0H
DSP control
DSPs and general control register
0FFFH
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