參數(shù)資料
型號: SAA7715AH
廠商: NXP SEMICONDUCTORS
元件分類: 數(shù)字信號處理
英文描述: Digital Signal Processor
中文描述: 0-BIT, 24.576 MHz, OTHER DSP, PQFP44
封裝: 10 X 10 MM, 1.75 MM HEIGHT, PLASTIC, SOT-307-2, QFP-44
文件頁數(shù): 18/36頁
文件大小: 167K
代理商: SAA7715AH
2003 Mar 13
18
Philips Semiconductors
Preliminary specification
Digital Signal Processor
SAA7715AH
9.8
I
2
C-bus memory map definition
Table 10
DSP and general control register (602FH)
Table 11
SPDIF IN channel status register 2 right (0FF2H)
Table 12
SPDIF IN channel status register 1 right (0FF3H)
NAME
SIZE
(BITS)
DESCRIPTION
DEFAULT
BIT
POSITION
1
5
1
reserved
PLL clock division factor according to Table 2
PLL output frequency
1: double
0: no doubling
reserved
program counter reset DSP
1: reset on
0: reset off
reserved
selection of n
×
f
s
clock at SYSCLK output according to
Table 4
word select input range selection for WS_PLL according
to Table 3
reserved
clock source for FSDAC
00: WS_PLL if no signal to pin CLK_IN
01: 512f
s
to pin CLK_IN
11: 256f
s
to pin CLK_IN
output on pin SYSCLK
1: disable
0: enable
signal on pin SYSCLK
1: fixed 256f
s
clock
0: n
×
f
s
clock; determined by bits 13 to 11
reserved
0
00011
1
0
5 to 1
6
pll_div[4:0]
dsp_turbo
1
1
1
0
7
8
pc_reset_dsp
2
3
00
010
10 to 9
13 to 11
sel[2:0]
sel_loop_div[1:0]
2
01
15 to 14
2
2
00
00
17 to 16
19 to 18
sel_FSDAC_clk
dis_SYSCLK
1
0
20
256f
s
_n*Fs
1
0
21
2
00
23 to 22
NAME
SIZE
(BITS)
DESCRIPTION
DEFAULT
BIT
POSITION
ch_stat_in right lsb
20
channel status SPDIF in right LSB bits 19 to 0
00000H
19 to 0
NAME
SIZE
(BITS)
DESCRIPTION
DEFAULT
BIT
POSITION
ch_stat_in right msb
20
channel status SPDIF in right MSB bits 39 to 20
00000H
19 to 0
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