參數(shù)資料
型號(hào)： SAA7740
廠商： NXP Semiconductors N.V.
英文描述： Digital Audio Processing IC DAPIC
中文描述： 數(shù)字音頻處理集成電路賈皮奇
文件頁(yè)數(shù)： 14/28頁(yè)
文件大?。?/td> 142K
代理商： SAA7740
1997 May 30
14
Philips Semiconductors
Product specification
Digital Audio Processing IC (DAPIC)
SAA7740H
DRAM interface
The DRAM interface contains a nibble wide data bus, a
9-bit wide address bus and all necessary control signals to
enable the different DRAM configurations.
Timing of the control signals RAS, CAS, CAS2, A8B, OE
and WE is related to the applied clock frequency of the
DAPIC. The important timing parameters are the page
mode cycle time (t
cy;CAS
), the access time (t
acc;RAS
), the
refreshing rate and the maximum value for RAS to CAS
delay time (t
dRAS;CAS
) (see Chapter “Timing
characteristics” and Fig.10). A read/write operation will
always be executed in the page mode (one row address
and four column addresses) because every data transfer
consists of 4 nibbles.
The refresh time of the DRAM (t
rfsh
) must be greater than;
where ‘a(chǎn)ddr’ is the number of physical address lines and
f
as
is measured in kHz.
t
rfsh
addr
3f
as
2
ms
>
For fast DRAMs, the maximum value for RAS to CAS
delay time (t
dRAS;CAS
) is important.
Different DRAM combinations can be connected to the
DAPIC. The smallest DRAM is a 64
×
4-bit (256 kbits)
RAM. For this configuration, 16K data words can be
stored. When this RAM is connected to the DAPIC, the
MSB address signal (A8) can be felt floating.
The DAPIC can address up to 1 Mbit DRAMs. However,
RAMs greater than 1 Mbit can also be connected. This,
therefore, implies that the redundant address lines of the
RAM must be fixed to V
DD
or V
SS
or must be joined with
one of the other address pins.
The choice of a 256 kbit or a 1 Mbit DRAM device must be
indicated by a flag bit residing in the start address control
word of the different delay lines.
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