參數(shù)資料
型號(hào)： SAB-C509-LM
廠(chǎng)商： INFINEON TECHNOLOGIES AG
英文描述： DBMM25SN
中文描述： 8位CMOS微控制器
文件頁(yè)數(shù)： 55/74頁(yè)
文件大小： 1607K
代理商： SAB-C509-LM
C509-L
Semiconductor Group
54
A/D Conversion Timing
An A/D conversion is internally started by writing into the SFR ADDATL with dummy data. A write
to SFR ADDATL will start a new conversion even if a conversion is currently in progress. Basically,
the A/D conversion procedure is divided into three parts :
– Sample phase (t
S
), used for sampling the analog input voltage.
– Conversion phase (t
CO
), used for the real A/D conversion.(includes calibration)
– Write result phase (t
WR
), used for writing the conversion result into the ADDAT registers.
The total A/D conversion time is defined by t
ADCC
which is the sum of the two phase times t
S
and
t
CO
. The duration of the two phases of an A/D conversion is specified by its specific timing
parameter as shown in
figure 29
.
Figure 29
A/D Conversion Timing
Conversion Clock
Prescaler
ADCL1 ADCL0
Sample Clock
Prescaler
ADST1 ADST0
Sample
Time
t
S
Conversion
Time
t
CO
ConversionTime
t
ADCC
Number of
CPU Cycles
0
0
0
0
1
1
0
1
0
1
8 x t
IN
16 x t
IN
32 x t
IN
64 x t
IN
16 x t
IN
32 x t
IN
64 x t
IN
128 x t
IN
32 x t
IN
64 x t
IN
128 x t
IN
256 x t
IN
64 x t
IN
128 x t
IN
256 x t
IN
512 x t
IN
40 x t
IN
48 x t
IN
56 x t
IN
72 x t
IN
104 x t
IN
96 x t
IN
112 x t
IN
144 x t
IN
208 x t
IN
192 x t
IN
224 x t
IN
288 x t
IN
416 x t
IN
384 x t
IN
448 x t
IN
576 x t
IN
832 x t
IN
8
9
12
17
0
1
0
0
1
1
0
1
0
1
80 x t
IN
16
18
24
34
1
0
0
0
1
1
0
1
0
1
160 x t
IN
32
37
48
69
1
1
0
0
1
1
0
1
0
1
320 x t
IN
64
74
96
138
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