參數(shù)資料
型號： SAF-C161S-LM 3V AA
廠商： Infineon Technologies
文件頁數(shù)： 44/75頁
文件大小： 0K
描述： IC MCU 16BIT ROM/LESS MQFP-80-7
標(biāo)準(zhǔn)包裝： 1
系列： C16xx
核心處理器： C166
芯體尺寸： 16-位
速度： 20MHz
連通性： EBI/EMI，SPI，UART/USART
外圍設(shè)備： POR，PWM，WDT
輸入/輸出數(shù)： 63
程序存儲(chǔ)器類型： ROMless
RAM 容量： 2K x 8
電壓 - 電源 (Vcc/Vdd)： 3 V ~ 3.6 V
振蕩器型： 外部
工作溫度： -40°C ~ 85°C
封裝/外殼： 80-QFP
包裝： 剪切帶 (CT)
其它名稱： SAF-C161S-LM3VAACT
SAF-C161S-LM3VAACT-ND
SAF-C161S-LM3VAAINCT
C161S
Timing Characteristics
Data Sheet
45
V1.0, 2003-11
levels present on the upper half of PORT0 (P0H), i.e. bitfield CLKCFG represents the
logic levels on pins P0.15-13 (P0H.7-5).
Table 13 associates the combinations of these three bits with the respective clock
generation mode.
Prescaler Operation
When prescaler operation is configured (CLKCFG = 001
B) the CPU clock is derived from
the internal oscillator (input clock signal) by a 2:1 prescaler.
The frequency of
f
CPU is half the frequency of fOSC and the high and low time of fCPU (i.e.
the duration of an individual TCL) is defined by the period of the input clock
f
OSC.
The timings listed in the AC Characteristics that refer to TCLs therefore can be
calculated using the period of
f
OSC for any TCL.
Phase Locked Loop
When PLL operation is configured (via CLKCFG) the on-chip phase locked loop is
enabled and provides the CPU clock (see Table 13). The PLL multiplies the input
frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e.
f
CPU
=
f
OSC × F). With every F’th transition of fOSC the PLL circuit synchronizes the CPU clock
to the input clock. This synchronization is done smoothly, i.e. the CPU clock frequency
does not change abruptly.
Due to this adaptation to the input clock the frequency of
f
CPU is constantly adjusted so
it is locked to
f
OSC. The slight variation causes a jitter of fCPU which also effects the
duration of individual TCLs.
Table 13
C161S Clock Generation Modes
CLKCFG
(P0H.7-5)
CPU Frequency
f
CPU = fOSC × F
External Clock
Input Range
1)
1) The external clock input range refers to a CPU clock range of 10 … 25 MHz (PLL operation). If the on-chip
oscillator is used together with a crystal, the oscillator frequency is limited to a range of 4 MHz to 16 MHz.
Notes
1 1 1
f
OSC × 4
2.5 to 6.25 MHz
Default configuration
1 1 0
f
OSC × 3
3.33 to 8.33 MHz
–
1 0 1
f
OSC × 2
5 to 12.5 MHz
–
1 0 0
f
OSC × 5
2 to 5 MHz
–
0 1 1
f
OSC × 1
1 to 25 MHz
Direct drive
2)
2) The maximum frequency depends on the duty cycle of the external clock signal.
0 1 0
f
OSC × 1.5
6.66 to 16.67 MHz
–
0 0 1
f
OSC / 2
2 to 50 MHz
CPU clock via prescaler
0 0 0
f
OSC × 2.5
4 to 10 MHz
–
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