參數(shù)資料
型號(hào): SAF-XE164K-48F66L
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 16-BIT, FLASH, MICROCONTROLLER, PQFP100
封裝: 0.50 MM PITCH, GREEN, PLASTIC, LQFP-100
文件頁數(shù): 40/113頁
文件大小: 1498K
代理商: SAF-XE164K-48F66L
XE164x
XE166 Family Derivatives
General Device Information
Preliminary
Data Sheet
30
V2.0, 2008-03
2,
25,
27,
50,
52,
75,
77,
100
V
DDPB
-
PS/B Digital Pad Supply Voltage for Domain B
Connect decoupling capacitors to adjacent
V
DDP/VSS pin pairs as close as possible to the pins.
Note: The on-chip voltage regulators and all ports
except P5, P6, and P15 are fed from supply
voltage
V
DDPB.
1,
26,
51,
76
V
SS
-
PS/-- Digital Ground
All
V
SS pins must be connected to the ground-line
or ground-plane.
Note: Also the exposed pad is connected to
V
SS.
The respective board area must be
connected to ground (if soldered) or left free.
1) To generate the reference clock output for bus timing measurement,
fSYS must be selected as source for
EXTCLK and P2.8 must be selected as output pin. Also the high-speed clock pad must be enabled. This
configuration is referred to as reference clock output signal CLKOUT.
2) Pin TRef was used to control the core voltage generation in step AA. For that step, pin TRef must be connected
to
V
DDPB.
This connection is no more required from step AB on. For the current step, pin TRef is logically not connected.
Future derivatives will feature an additional general purpose IO pin at this position.
Table 4
Pin Definitions and Functions (cont’d)
Pin
Symbol
Ctrl.
Type Function
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