參數(shù)資料
型號(hào)： SAH-XC2723X-20F66V
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQCC48
封裝： 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁數(shù)： 37/112頁
文件大?。?/td> 3116K
代理商： SAH-XC2723X-20F66V
XC2723X
XC2000 Family / Econo Line
Functional Description
PRELIMINARY
Data Sheet
26
V1.0, 2010-12
3.1
Memory Subsystem and Organization
The memory space of the XC2723X is configured in the von Neumann architecture. In
this architecture all internal and external resources, including code memory, data
memory, registers and I/O ports, are organized in the same linear address space.
Table 8
XC2723X Memory Map 1)
Address Area
Start Loc. End Loc.
Area Size2)
Notes
IMB register space
FF’FF00H FF’FFFFH 256 bytes
Reserved
F0’0000H FF’FEFFH < 1 Mbyte
Minus IMB
registers.
Reserved for EPSRAM
E8’1000H EF’FFFFH 508 Kbytes
Mirrors EPSRAM
Emulated PSRAM
E8’0000H E8’0FFFH up to 4 Kbytes With Flash timing.
Reserved for PSRAM
E0’1000H E7’FFFFH 508 Kbytes
Mirrors PSRAM
PSRAM
E0’0000H E0’0FFFH up to 4 Kbytes Program SRAM.
Reserved for Flash
C4’8000H DF’FFFFH 1760 Kbytes
Flash 1
C4’0000H C4’7FFFH 32 Kbytes
Reserved for Flash
C2’1000H C3’FFFFH 124 Kbytes
Flash 0
C0’0000H C2’0FFFH 132 Kbytes
3)
External memory area
40’0000H BF’FFFFH 8 Mbytes
External IO area4)
21’0000H 3F’FFFFH 1984 Kbytes
Reserved
20’B800H 20’FFFFH 18 Kbytes
USIC0-1 alternate regs.
20’B000H 20’B7FFH 2 Kbytes
Accessed via
LXBus Controller
MultiCAN alternate regs. 20’8000H 20’AFFFH 12 Kbytes
Accessed via
LXBus Controller
Reserved
20’5000H 20’7FFFH 12 Kbytes
USIC0-1 registers
20’4000H 20’4FFFH 4 Kbytes
Accessed via
LXBus Controller
MultiCAN registers
20’0000H 20’3FFFH 16 Kbytes
Accessed via
LXBus Controller
External memory area
01’0000H 1F’FFFFH 1984 Kbytes
SFR area
00’FE00H 00’FFFFH 0.5 Kbytes
Dual-port RAM
(DPRAM)
00’F600H 00’FDFFH 2 Kbytes
Reserved for DPRAM
00’F200H 00’F5FFH 1 Kbytes
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