參數(shù)資料
型號(hào): SAH-XC2723X-20F66V
廠商: INFINEON TECHNOLOGIES AG
元件分類: 微控制器/微處理器
英文描述: 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PQCC48
封裝: 0.50 MM PITCH, GREEN, PLASTIC, VQFN-48
文件頁(yè)數(shù): 63/112頁(yè)
文件大?。?/td> 3116K
代理商: SAH-XC2723X-20F66V
XC2723X
XC2000 Family / Econo Line
Functional Description
PRELIMINARY
Data Sheet
50
V1.0, 2010-12
When clocked by
f
SYS = 80 MHz, time intervals between 12.5 ns and 13.4 s can be
monitored.
When clocked by
f
WU = 500 kHz, time intervals between 2.0 s and 2147.5 s can be
monitored.
The default Watchdog Timer interval after power-up is 0.13 s (@
f
WU = 500 kHz).
3.16
Clock Generation
The Clock Generation Unit can generate the system clock signal
f
SYS for the XC2723X
from a number of external or internal clock sources:
External clock signals with pad voltage or core voltage levels
External crystal or resonator using the on-chip oscillator
On-chip clock source for operation without crystal/resonator
Wake-up clock (ultra-low-power) to further reduce power consumption
The programmable on-chip PLL with multiple prescalers generates a clock signal for
maximum system performance from standard crystals, a clock input signal, or from the
on-chip clock source. See also Section 4.6.2.
The Oscillator Watchdog (OWD) generates an interrupt if the crystal oscillator frequency
falls below a certain limit or stops completely. In this case, the system can be supplied
with an emergency clock to enable operation even after an external clock failure.
All available clock signals can be output on the EXTCLK pin.
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