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參數(shù)資料
| 型號： | SAK-C509-LM |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, 16 MHz, MICROCONTROLLER, PQFP100 |
| 封裝： | PLASTIC, MQFP-100 |
| 文件頁數(shù)： | 17/74頁 |
| 文件大?。?/td> | 1607K |
| 代理商： | SAK-C509-LM |
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Semiconductor Group
23
09.96
C509-L
Control of XRAM Access
The XRAM in the C509-L is a memory area that is logically located at the upper end of the external
memory space, but is integrated on the chip. Because the XRAM is used in the same way as
external data memory the same instruction types (MOVX) must be used for accessing the XRAM.
Two bits in SFR SYSCON, XMAP0 and XMAP1, control the accesses to the XRAM.
Special Function Register SYSCON (Address B1H)
Reset Value : 1010XX01B
Bit XMAP0 is hardware protected. If it is reset once (XRAM access enabled) it cannot be set by
software. Only a reset operation will set the XMAP0 bit again.
The XRAM can be accessed by read/write instructions (MOVX A,DPTR, MOVX @DPTR,A), which
use the 16-bit DPTR for indirect addressing. For accessing the XRAM, the effective address stored
in DPTR must be in the range of F700H to FFFFH.38
The XRAM can be also accessed by read/write instructions (MOVX A,@Ri, MOVX @Ri,A), which
use only an 8-bit address (indirect addressing with registers R0 or R1). Therefore, a special page
register XPAGE which provides the upper address information (A8-A15) during 8-bit XRAM
accesses.
The behaviour of Port 0 and P2 during a MOVX access depends on the control bits XMAP0 and
XMAP1 in register SYSCON and on the state of pin EA. Table 3 lists the various operating
conditions.
Bit
Function
XMAP1
XRAM visible access control
Control bit for RD/WR signals during XRAMaccesses. If addresses are
outside the XRAM address range or if XRAM is disabled, this bit has no
effect.
XMAP1 = 0 : The signals RD and WR are not activated during accesses to
the XRAM
XMAP1 = 1 : Ports 0, 2 and the signals RD and WR are activated during
accesses to XRAM. In this mode, address and data
information during XRAM/CAN Controller accesses are
visible externally.
XMAP0
Global XRAM access enable/disable control
XMAP0 = 0 : The access to XRAM is enabled.
XMAP0 = 1 : The access to XRAM is disabled (default after reset!).
All MOVX accesses are performed via the external bus.
Further, this bit is hardware protected.
76543210
1
RMAP
–
B1H
SYSCON
Bit No.
MSB
LSB
–
XMAP1
CLKP
PMOD
XMAP0
The functions of the shaded bits are not used for XRAM control.
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