參數(shù)資料
型號(hào)： SAK-XC164LM-16F20F
廠商： INFINEON TECHNOLOGIES AG
元件分類(lèi)： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TQFP-64
文件頁(yè)數(shù)： 20/60頁(yè)
文件大?。?/td> 1415K
代理商： SAK-XC164LM-16F20F
XC164LM
Derivatives
Functional Description
Preliminary
Data Sheet
25
V1.1, 2006-08
3.5
Capture/Compare Unit (CAPCOM2)
The CAPCOM unit supports generation and control of timing sequences on up to
16 channels with a maximum resolution of 1 system clock cycle (8 cycles in staggered
mode). The CAPCOM unit is typically used to handle high speed I/O tasks such as pulse
and waveform generation, pulse width modulation (PWM), Digital to Analog (D/A)
conversion, software timing, or time recording relative to external events.
Two 16-bit timers (T7/T8) with reload registers provide two independent time bases for
the capture/compare register array.
The input clock for the timers is programmable to several prescaled values of the internal
system clock, or may be derived from an overflow/underflow of timer T6 in module GPT2.
This provides a wide range of variation for the timer period and resolution and allows
precise adjustments to the application specific requirements. In addition, an external
count input for CAPCOM timer T7 allows event scheduling for the capture/compare
registers relative to external events.
The capture/compare register array contains 16 dual purpose capture/compare
registers, each of which may be individually allocated to either CAPCOM timer (T7 or T8,
respectively), and programmed for capture or compare function.
10 registers of the CAPCOM2 module have each one port pin associated with it which
serves as an input pin for triggering the capture function, or as an output pin to indicate
the occurrence of a compare event.
When a capture/compare register has been selected for capture mode, the current
contents of the allocated timer will be latched (‘captured’) into the capture/compare
Table 6
Compare Modes (CAPCOM2)
Compare Modes
Function
Mode 0
Interrupt-only compare mode;
Several compare interrupts per timer period are possible
Mode 1
Pin toggles on each compare match;
Several compare events per timer period are possible
Mode 2
Interrupt-only compare mode;
Only one compare interrupt per timer period is generated
Mode 3
Pin set ‘1’ on match; pin reset ‘0’ on compare timer overflow;
Only one compare event per timer period is generated
Double Register
Mode
Two registers operate on one pin;
Pin toggles on each compare match;
Several compare events per timer period are possible
Single Event Mode
Generates single edges or pulses;
Can be used with any compare mode
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