參數(shù)資料
型號(hào)： SAK-XC164LM-16F20F
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 16-BIT, FLASH, 20 MHz, MICROCONTROLLER, PQFP64
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TQFP-64
文件頁數(shù)： 50/60頁
文件大?。?/td> 1415K
代理商： SAK-XC164LM-16F20F
XC164LM
Derivatives
Electrical Parameters
Preliminary
Data Sheet
52
V1.1, 2006-08
This is especially important for bus cycles using waitstates and e.g. for the operation of
timers, serial interfaces, etc. For all slower operations and longer periods (e.g. pulse train
generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter
is negligible.
The value of the accumulated PLL jitter depends on the number of consecutive VCO
output cycles within the respective timeframe. The VCO output clock is divided by the
output prescaler (K = PLLODIV+1) to generate the master clock signal
f
MC. Therefore,
the number of VCO cycles can be represented as K
× N, where N is the number of
consecutive
f
MC cycles (TCM).
For a period of N
× TCM the accumulated PLL jitter is defined by the deviation D
N:
DN [ns] = ±(1.5 + 6.32 × N / fMC); fMC in [MHz], N = number of consecutive TCMs.
So, for a period of 3 TCMs @ 20 MHz and K = 12: D3 = ±(1.5 + 6.32 × 3 / 20) = 2.448 ns.
This formula is applicable for K
× N < 95. For longer periods the K × N = 95 value can be
used. This steady value can be approximated by: DNmax [ns] = ±(1.5 + 600 / (K × fMC)).
Figure 13
Approximated Accumulated PLL Jitter
Note: The bold lines indicate the minimum accumulated jitter which can be achieved by
selecting the maximum possible output prescaler factor K.
MCD05566
N
0
±1
±2
±3
±4
±5
±6
±7
±8
Acc. jitter
D
N
05
10
15
20
25
ns
K = 15
K = 12
K = 10
K = 8
K = 6 K = 5
1
10 MHz
20 MHz
40 MHz
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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