參數(shù)資料
型號(hào)： SAK-XC2712X-8F66R
廠商： INFINEON TECHNOLOGIES AG
元件分類： 微控制器/微處理器
英文描述： 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38
封裝： 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38
文件頁數(shù)： 44/103頁
文件大?。?/td> 2957K
代理商： SAK-XC2712X-8F66R
XC2712X
XC2000 Family / Compact Line
Functional Description
PRELIMINARY
Data Sheet
41
V1.0, 2010-12
3.12
Universal Serial Interface Channel Modules (USIC)
The XC2712X features the USIC module USIC0. The module provides two serial
communication channels.
The Universal Serial Interface Channel (USIC) module is based on a generic data shift
and data storage structure which is identical for all supported serial communication
protocols. Each channel supports complete full-duplex operation with a basic data buffer
structure (one transmit buffer and two receive buffer stages). In addition, the data
handling software can use FIFOs.
The protocol part (generation of shift clock/data/control signals) is independent of the
general part and is handled by protocol-specific preprocessors (PPPs).
The USIC’s input/output lines are connected to pins by a pin routing unit. The inputs and
outputs of each USIC channel can be assigned to different interface pins, providing great
flexibility to the application software. All assignments can be made during runtime.
Figure 10
General Structure of a USIC Module
The regular structure of the USIC module brings the following advantages:
Higher flexibility through configuration with same look-and-feel for data management
Reduced complexity for low-level drivers serving different protocols
Wide range of protocols with improved performances (baud rate, buffer handling)
USIC_basic.vsd
Bu
sI
n
te
rf
ac
e
DBU
0
DBU
1
Control 0
Control 1
DSU
0
DSU
1
PPP_A
PPP_B
PPP_C
PPP_D
PPP_A
PPP_B
PPP_C
PPP_D
P
in
R
o
ut
in
g
S
h
el
l
Buffer & Shift Structure Protocol Preprocessors
Pins
Bus
fsys
Fractional
Dividers
Baud rate
Generators
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