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參數(shù)資料
| 型號(hào)： | SAK-XC2712X-8F66R |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, FLASH, 66 MHz, RISC MICROCONTROLLER, PDSO38 |
| 封裝： | 0.50 MM PITCH, GREEN, PLASTIC, TSSOP-38 |
| 文件頁數(shù)： | 45/103頁 |
| 文件大?。?/td> | 2957K |
| 代理商： | SAK-XC2712X-8F66R |
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XC2712X
XC2000 Family / Compact Line
Functional Description
PRELIMINARY
Data Sheet
42
V1.0, 2010-12
Target Protocols
Each USIC channel can receive and transmit data frames with a selectable data word
width from 1 to 16 bits in each of the following protocols:
UART (asynchronous serial channel)
– module capability: maximum baud rate =
f
SYS / 4
– data frame length programmable from 1 to 63 bits
– MSB or LSB first
LIN Support (Local Interconnect Network)
– module capability: maximum baud rate =
f
SYS / 16
– checksum generation under software control
– baud rate detection possible by built-in capture event of baud rate generator
SSC/SPI/QSPI (synchronous serial channel with or without data buffer)
– module capability: maximum baud rate =
f
SYS / 2, limited by loop delay
– number of data bits programmable from 1 to 63, more with explicit stop condition
– MSB or LSB first
– optional control of slave select signals
IIC (Inter-IC Bus)
– supports baud rates of 100 kbit/s and 400 kbit/s
IIS (Inter-IC Sound Bus)
– module capability: maximum baud rate =
f
SYS / 2
Note: Depending on the selected functions (such as digital filters, input synchronization
stages, sample point adjustment, etc.), the maximum achievable baud rate can be
limited. Please note that there may be additional delays, such as internal or
external propagation delays and driver delays (e.g. for collision detection in UART
mode, for IIC, etc.).
3.13
System Timer
The System Timer consists of a programmable prescaler and two concatenated timers
(10 bits and 6 bits). Both timers can generate interrupt requests. The clock source can
be selected and the timers can also run during power reduction modes.
Therefore, the System Timer enables the software to maintain the current time for
scheduling functions or for the implementation of a clock.
3.14
Window Watchdog Timer
The Window Watchdog Timer is one of the fail-safe mechanisms which have been
implemented to prevent the controller from malfunctioning for longer periods of time.
The Window Watchdog Timer is always enabled after an application reset of the chip. It
can be disabled and enabled at any time by executing the instructions DISWDT and
ENWDT respectively. The software has to service the Window Watchdog Timer before
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