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參數(shù)資料
| 型號(hào)： | SB-36210IA-361N |
| 廠商： | DATA DEVICE CORP |
| 元件分類： | 位置變換器 |
| 英文描述： | SYNCHRO OR RESOLVER TO DIGITAL CONVERTER, DMA34 |
| 封裝： | MODULE, PACKAGE-34 |
| 文件頁(yè)數(shù)： | 7/11頁(yè) |
| 文件大?。?/td> | 237K |
| 代理商： | SB-36210IA-361N |
5
Data Device Corporation
www.ddc-web.com
SB-36210IX
J-01/06-0
HARDWARE CONFIGURATION
The SB-36210IX is a PCI device, and as such does not require
jumpers or switches to set the Base address or interrupt values.
The job of configuration for Plug-and-Play PCI configuration is
performed by the PC BIOS. During the initial power on boot
process, the BIOS performs an enumeration of the PCI bus and
provides a configuration in the system that satisfies the card
requirements. The card provides the BIOS with details of how
much memory it requires, and any other operating parameters
that the system needs to know by way of configuration registers
built into the card. These registers are configured at the factory
to contain the optimum values for the operation of the SB-
36210IX. The SB-36210IX PCI card and software drivers allow
for shared interrupts, thus simplifying the installation and reduc-
ing the risk of device conflicts.
BUILT-IN-TEST
The Built-In-Test (BIT) will flag Loss-of-Signal (LOS) and Loss-
of-Reference (LOR) fault conditions. Also, excessive error is
detected by monitoring the demodulator output, which is propor-
tional to the difference between the analog input and the digital
output. When it exceeds approximately 100 LSB’s (in the select-
ed resolution), the BIT will be asserted. This condition can occur
any time the analog input changes at a rate in excess of the max-
imum tracking rate. During power up the converter may see a
large difference between the sin/cos inputs and the digital output
angle held in its counter. BIT will be asserted until the converter
settles within -100 LSB’s of the final result.
SYNTHESIZED REFERENCE
The synthesized reference eliminates errors due to phase shift
between the reference and the signal inputs up to 45°.
Quadrature voltages in a Resolver or Synchro are, by definition,
the resulting 90° fundamental signal in the nulled out error volt-
age (e) in the converter. Due to the inductive nature of resolvers
and synchros, their output signals lead the reference input signal
(RH and RL). When an uncompensated reference signal is used
to demodulate the control transformer’s output, Quadrature volt-
ages are not completely eliminated. Therefore this is the perfect
solution to combat phase shift error to 45°.
ON-BOARD INTERNAL REFERENCE
OSCILLATOR
The on-board oscillator may be used to take the place of an
external drive oscillator for the excitation signal. This oscillator is
available in several options, see the ordering information page
for details. Depending on oscillator selected, there are three pro-
grammable voltage ranges.
TWO SPEED
Two speed allows resolutions greater than 16 bits to be achieved.
See “CalculateTwoSpeed” in Appendix A of the card manual for
details. Also refer to the RD/RDC Applications manual (MN-
19220XX-001) and the Synchro/Resolver Conversion Handbook.
These documents are available at www.ddc-web.com.
INTERNAL INCREMENTAL OPTICAL ENCODER
EMULATION
The card can be programmed to encoder emulation mode. These
outputs are available on the 68-pin mini D connector “A” and “B”. ZI
is the zero index. The timing of the A, B output is dependent on the
rate of change of the Synchro/Resolver position (rps or degrees per
second) and the encoder resolution latched into the converter.
RD-19230
1 MSB
2
3
4
9
10
11
12
13
14
15
BIT 16 LSB
B
1
0
1
2
1
4
1
6
A
5
6
7
8
FIGURE 4. INCREMENTAL ENCODER EMULATION RESOLUTION CONTROL
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