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參數(shù)資料
| 型號(hào)： | SC14422VJG |
| 廠商： | NATIONAL SEMICONDUCTOR CORP |
| 元件分類： | 無(wú)繩電話/電話 |
| 英文描述： | Complete Baseband Processor for DECT Base Stations |
| 中文描述： | TELECOM, CORDLESS, BASEBAND CIRCUIT, PQFP100 |
| 封裝： | TQFP-100 |
| 文件頁(yè)數(shù)： | 4/7頁(yè) |
| 文件大?。?/td> | 82K |
| 代理商： | SC14422VJG |
Copyright 1998 National Semiconductor Corp.
4
www.national.com
2.0 Pin Description
Table 1:
Pin Description)
PIN NAME
NR
TYPE
DESCRIPTION
SCLK
1
1
OUTPUT/INPUT. CR16A bus interface System CLocK output. In core mode this pin
is input.
Digital supply voltage
Digital ground
TRI-STATE OUTPUT. Programmable Power Down pins 7 to 0 to radio interface.
PD7,6 have 12 mA drive.
OUTPUT (Slope controlled). 10.368 MHz clock output. Logic ‘0’ after reset or when
disabled.
OUTPUT. Programmable Load Enable for synthesizer. Can be synchronized to
LKD input.
TRI-STATE OUTPUT. Serial data output.
OUTPUT. Serial interface clock: 1.152 MHz
TRI-STATE OUTPUT. Comparator output pin.
INPUT. Received Data. The polarity of this input is programmable.
INPUT. Comparator reference level. Internally a six bit DAC can be connected to
this pin to compensate for DC offsets.
INPUT. Receiver Signal Strength Indication. This signal is connected to a 6-bit ADC
input with peak hold circuitry. PD0 internally controls the peak hold circuitry. If PD0
is low RSSI is sampled, else the RSSI input will be connected to ground.
Analog supply voltage.
Analog ground.
TRI-STATE OUTPUT. Transmit Data. The polarity of this output is programmable.
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. UART data output.
INPUT/OUTPUT with selectable pull down resistor. General purpose memory
mapped I/O port bit. UART data input.
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. Multi function Chip select output CS0
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. Multi function Chip select output CS1
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. Multi function Chip select output CS2
INPUT/OUTPUT with selectable pull down resistor. General purpose memory
mapped I/O port bit. OUTPUT Address bit 18.
INPUT/OUTPUT with selectable pull down resistor. General purpose memory
mapped I/O port bit. OUTPUT Address bit 19.
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. OUTPUT 100 Hz clock synchronized to 10 msec frame.
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. Level sensitive interrupt source P10_INT
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. SPI Clock input/output
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. SPI Clock enable input if SPI slave. If SPI master this pin must
be set/reset by software.
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. SPI data input
INPUT/OUTPUT with selectable pull up resistor. General purpose memory
mapped I/O port bit. SPI data output
VDD
VSS
PD
7..0
2
3
4-11
5
RFCLK
12
5b
MEN1n
13
5
SO
SK
CMPOUT
RDI
CMPREF
14
15
16
17
18
1
5
1
analog
analog
RSSI
19
analog
AVD
AVS
TDO
P0[0] or
UTX
P0[1] or
URX
P0[2] or
CS0
P0[3] or
CS1
P0[4] or
CS2
P0[5] or
AD18
P0[6] or
AD19
P0[7] or
CLK100
P1[0] or
P10_INT
P1[1] or
SCK
P1[2] or
SEN
20
21
22
23
5/analog
2
24
3
25
2
26
2
27
2
28
3
29
3
30
2
31
2
32
2
33
2
P1[3] or
SDI
P1[4] or
SDO
34
2
35
2
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