- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄1967 > SC16C2552BIA44,529 (NXP Semiconductors)IC UART DUAL W/FIFO 44-PLCC PDF資料下載
參數(shù)資料
| 型號(hào)： | SC16C2552BIA44,529 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 7/37頁 |
| 文件大小： | 0K |
| 描述： | IC UART DUAL W/FIFO 44-PLCC |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 26 |
| 特點(diǎn)： | 2 通道 |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 44-LCC（J 形引線） |
| 供應(yīng)商設(shè)備封裝： | 44-PLCC |
| 包裝： | 管件 |
| 產(chǎn)品目錄頁面： | 828 (CN2011-ZH PDF) |
| 其它名稱： | 568-3646-5 935274408529 SC16C2552BIA44-S |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁
SC16C2552B_3
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 03 — 12 February 2009
15 of 38
NXP Semiconductors
SC16C2552B
5 V, 3.3 V and 2.5 V dual UART, 5 Mbit/s (max.), with 16-byte FIFOs
3
(continued)
Transmit operation in mode ‘1’: When the SC16C2552B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1), the TXRDYn pin will be a
logic 1 when the transmit FIFO is completely full. It will be a logic 0 if
one or more FIFO locations are empty.
Receive operation in mode ‘1’: When the SC16C2552B is in FIFO
mode (FCR[0] = logic 1; FCR[3] = logic 1) and the trigger level has been
reached, or a Receive Time-out has occurred, the RXRDY signal at the
MFn pin will go to a logic 0. Once activated, it will go to a logic 1 after
there are no more characters in the FIFO. Note that the AFR register
must be set to the RXRDY mode prior to any possible reading of the
RXRDY signal.
2
FCR[2]
XMIT FIFO reset.
logic 0 = no FIFO transmit reset (normal default condition)
logic 1 = clears the contents of the transmit FIFO and resets the FIFO
counter logic (the Transmit Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO.
1
FCR[1]
RCVR FIFO reset.
logic 0 = no FIFO receive reset (normal default condition)
logic 1 = clears the contents of the receive FIFO and resets the FIFO
counter logic (the Receive Shift Register is not cleared or altered).
This bit will return to a logic 0 after clearing the FIFO.
0
FCR[0]
FIFOs enabled.
logic 0 = disable the transmit and receive FIFO (normal default
condition)
logic 1 = enable the transmit and receive FIFO. This bit must be a ‘1’
when other FCR bits are written to or they will not be
programmed.
Table 9.
RCVR trigger levels
FCR[7]
FCR[6]
RX FIFO trigger level
0001
0104
1008
1114
Table 8.
FIFO Control Register bits description …continued
Bit
Symbol
Description
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| SC16C550BIB48,157 | IC UART SINGLE W/FIFO 48-LQFP |
| SC16C554DBIA68,529 | IC UART QUAD W/FIFO 68-PLCC |
| SC16C554IB80,528 | IC UART QUAD SOT315-1 |
| SC16C650BIB48,151 | IC UART SINGLE W/FIFO 48-LQFP |
| SC16C652BIB48,157 | IC ENCODER/DECODER IRDA 48LQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C2552BIA44-T | 功能描述:UART 接口集成電路 16CB 2.5V-5V 2CH UART 16B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C2552CIA44,512 | 制造商:NXP Semiconductors 功能描述: 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBEDP// - Rail/Tube |
| SC16C2552CIA44,518 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/REEL13DP// - Tape and Reel |
| SC16C2552CIA44,529 | 制造商:NXP Semiconductors 功能描述:SC16C2552CIA44/PLCC44/TUBESMDP// - Rail/Tube |
| SC16C2552IA44 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Dual UART with 16-byte transmit and receive FIFOs |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。