參數(shù)資料
型號: SC16C554DBIB64,157
廠商: NXP Semiconductors
文件頁數(shù): 17/57頁
文件大小: 0K
描述: IC UART QUAD W/FIFO 64-LQFP
標(biāo)準(zhǔn)包裝: 800
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 935276669157
SC16C554DBIB64
SC16C554DBIB64-ND
2010-2012 Microchip Technology Inc.
DS41413C-page 25
PIC12(L)F1822/PIC16(L)F1823
3.2.2
SPECIAL FUNCTION REGISTER
The Special Function Registers are registers used by
the application to control the desired operation of
peripheral functions in the device. The registers asso-
ciated with the operation of the peripherals are
described in the appropriate peripheral chapter of this
data sheet.
3.2.3
GENERAL PURPOSE RAM
There are up to 80 bytes of GPR in each data memory
bank.
3.2.3.1
Linear Access to GPR
The general purpose RAM can be accessed in a
non-banked method via the FSRs. This can simplify
access to large memory structures. See Section 3.5.2
for more information.
3.2.4
COMMON RAM
There are 16 bytes of common RAM accessible from all
banks.
FIGURE 3-2:
BANKED MEMORY
PARTITIONING
3.2.5
DEVICE MEMORY MAPS
The memory maps for the device family are as shown
0Bh
0Ch
1Fh
20h
6Fh
70h
7Fh
00h
Common RAM
(16 bytes)
General Purpose RAM
(80 bytes maximum)
Core Registers
(12 bytes)
Special Function Registers
(20 bytes maximum)
Memory Region
7-bit Bank Offset
TABLE 3-2:
MEMORY MAP TABLES
Device
Banks
Table No.
PIC12(L)F1822
PIC16(L)F1823
0-7
8-15
16-23
24-31
31
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