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參數(shù)資料
型號(hào): SC16C554DBIB64,157
廠商: NXP Semiconductors
文件頁(yè)數(shù): 30/57頁(yè)
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 64-LQFP
標(biāo)準(zhǔn)包裝: 800
通道數(shù): 4,QUART
FIFO's: 16 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測(cè)功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類(lèi)型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤(pán)
其它名稱(chēng): 935276669157
SC16C554DBIB64
SC16C554DBIB64-ND
2010-2012 Microchip Technology Inc.
DS41413C-page 37
PIC12(L)F1822/PIC16(L)F1823
Bank 6
300h(1)
INDF0
Addressing this location uses contents of FSR0H/FSR0L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
301h(1)
INDF1
Addressing this location uses contents of FSR1H/FSR1L to address data memory
(not a physical register)
xxxx xxxx xxxx xxxx
302h(1)
PCL
Program Counter (PC) Least Significant Byte
0000 0000 0000 0000
303h(1)
STATUS
—TO
PD
ZDC
C
---1 1000 ---q quuu
304h(1)
FSR0L
Indirect Data Memory Address 0 Low Pointer
0000 0000 uuuu uuuu
305h(1)
FSR0H
Indirect Data Memory Address 0 High Pointer
0000 0000 0000 0000
306h(1)
FSR1L
Indirect Data Memory Address 1 Low Pointer
0000 0000 uuuu uuuu
307h(1)
FSR1H
Indirect Data Memory Address 1 High Pointer
0000 0000 0000 0000
308h(1)
BSR
BSR<4:0>
---0 0000 ---0 0000
309h(1)
WREG
Working Register
0000 0000 uuuu uuuu
30Ah(1)
PCLATH
Write Buffer for the upper 7 bits of the Program Counter
-000 0000 -000 0000
30Bh(1)
INTCON
GIE
PEIE
TMR0IE
INTE
IOCIE
TMR0IF
INTF
IOCIF
0000 000x 0000 000u
30Ch
Unimplemented
30Dh
Unimplemented
30Eh
Unimplemented
30Fh
Unimplemented
310h
Unimplemented
311h
Unimplemented
312h
Unimplemented
313h
Unimplemented
314h
Unimplemented
315h
Unimplemented
316h
Unimplemented
317h
Unimplemented
318h
Unimplemented
319h
Unimplemented
31Ah
Unimplemented
31Bh
Unimplemented
31Ch
Unimplemented
31Dh
Unimplemented
31Eh
Unimplemented
31Fh
Unimplemented
TABLE 3-8:
SPECIAL FUNCTION REGISTER SUMMARY (CONTINUED)
Address
Name
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Value on
POR, BOR
Value on all
other
Resets
Legend:
x
= unknown, u = unchanged, q = value depends on condition, - = unimplemented, r = reserved.
Shaded locations are unimplemented, read as ‘0’.
Note
1:
These registers can be addressed from any bank.
2:
PIC16(L)F1823 only.
3:
Unimplemented. Read as ‘1’.
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