參數資料
| 型號： | SC16C554IB80,528 |
| 廠商： | NXP Semiconductors |
| 文件頁數： | 26/55頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART QUAD SOT315-1 |
| 標準包裝： | 1 |
| 通道數： | 4，QUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動流量控制功能： | 是 |
| 帶IrDA 編碼器/解碼器： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調制解調器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 80-LQFP |
| 供應商設備封裝： | 80-LQFP（12x12） |
| 包裝： | 標準包裝 |
| 其它名稱： | 568-5954-6 |
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Philips Semiconductors
SC16C554/554D
Quad UART with 16-byte FIFO and infrared (IrDA) encoder/decoder
Product data
Rev. 05 — 10 May 2004
32 of 55
9397 750 13132
Koninklijke Philips Electronics N.V. 2004. All rights reserved.
7.8 Modem Status Register (MSR)
This register provides the current state of the control interface signals from the
modem, or other peripheral device to which the SC16C554/554D is connected.
Four bits of this register are used to indicate the changed information. These bits are
set to a logic 1 whenever a control input from the modem changes state. These bits
are set to a logic 0 whenever the CPU reads this register.
0
LSR[0]
Receive data ready.
Logic 0 = No data in receive holding register or FIFO (normal default
condition).
Logic 1 = Data has been received and is saved in the receive holding
register or FIFO.
Table 19:
Line Status Register bits description…continued
Bit
Symbol
Description
Table 20:
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (Active-HIGH, logical 1). Normally this bit is the complement of the
CD input. In the loop-back mode this bit is equivalent to the OP2 bit in the
MCR register.
6
MSR[6]
RI (Active-HIGH, logical 1). Normally this bit is the complement of the RI
input. In the loop-back mode this bit is equivalent to the OP1 bit in the
MCR register.
5
MSR[5]
DSR (Active-HIGH, logical 1). Normally this bit is the complement of the
DSR input. In loop-back mode this bit is equivalent to the DTR bit in the
MCR register.
4
MSR[4]
CTS. CTS functions as hardware ow control signal input if it is enabled
via EFR[7]. The transmit holding register ow control is enabled/disabled
by MSR[4]. Flow control (when enabled) allows starting and stopping the
transmissions based on the external modem CTS signal. A logic 1 at the
CTS pin will stop SC16C554/554D transmissions as soon as current
character has nished transmission. Normally MSR[4] is the complement
of the CTS input. However, in the loop-back mode, this bit is equivalent to
the RTS bit in the MCR register.
3
MSR[3]
CD [1]
Logic 0 = No CD change (normal default condition).
Logic1=The CD input to the SC16C554/554D has changed state
since the last time it was read. A modem Status Interrupt will be
generated.
2
MSR[2]
RI [1]
Logic 0 = No RI change (normal default condition).
Logic1=The RI input to the SC16C554/554D has changed from a
logic 0 to a logic 1. A modem Status Interrupt will be generated.
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