參數(shù)資料
型號: SC16C650BIB48,151
廠商: NXP Semiconductors
文件頁數(shù): 11/48頁
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 250
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 管件
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
19 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.3 FIFO Control Register (FCR)
This register is used to enable the FIFOs, clear the FIFOs, set the receive FIFO trigger
levels, and select the DMA mode.
7.3.1 DMA mode
7.3.1.1
Mode 0 (FCR bit 3 = 0)
Set and enable the interrupt for each single transmit or receive operation, and is similar to
the 16C450 mode. Transmit Ready (TXRDY) will go to a logic 0 whenever an empty
transmit space is available in the Transmit Holding Register (THR). Receive Ready
(RXRDY) will go to a logic 0 whenever the Receive Holding Register (RHR) is loaded with
a character.
7.3.1.2
Mode 1 (FCR bit 3 = 1)
Set and enable the interrupt in a block mode operation. The transmit interrupt is set when
the transmit FIFO is below the programmed trigger level. The receive interrupt is set when
the receive FIFO lls to the programmed trigger level. However, the FIFO continues to ll
regardless of the programmed level until the FIFO is full. RXRDY remains a logic 0 as long
as the FIFO ll level is above the programmed trigger level.
7.3.2 FIFO mode
Table 10.
FIFO Control Register bits description
Bit
Symbol
Description
7:6
FCR[7] (MSB),
FCR[6] (LSB)
RCVR trigger. These bits are used to set the trigger level for the receive
FIFO interrupt.
An interrupt is generated when the number of characters in the FIFO
equals the programmed trigger level. However, the FIFO will continue to
be loaded until it is full. Refer to Table 11.
5:4
FCR[5] (MSB),
FCR[4] (LSB)
Logic 0 or cleared is the default condition; TX trigger level = 16.
These bits are used to set the trigger level for the transmit FIFO
interrupt. The SC16C650B will issue a transmit empty interrupt when
the number of characters in FIFO drops below the selected trigger level.
Refer to Table 12.
3
FCR[3]
DMA mode select.
logic 0 = set DMA mode ‘0’ (normal default condition)
logic 1 = set DMA mode ‘1’
Transmit operation in mode ‘0’: When the SC16C650B is in the
16C450 mode (FIFOs disabled; FCR[0] = logic 0) or in the FIFO mode
(FIFOs enabled; FCR[0] = logic 1; FCR[3] = logic 0), and when there
are no characters in the transmit FIFO or transmit holding register, the
TXRDY pin will be a logic 0. Once active, the TXRDY pin will go to a
logic 1 after the rst character is loaded into the transmit holding
register.
Receive operation in mode ‘0’: When the SC16C650B is in 16C450
mode, or in the FIFO mode (FCR[0] = logic 1; FCR[3] = logic 0) and
there is at least one character in the receive FIFO, the RXRDY pin will
be a logic 0. Once active, the RXRDY pin will go to a logic 1 when there
are no more characters in the receiver.
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