參數(shù)資料
型號: SC16C650BIB48,151
廠商: NXP Semiconductors
文件頁數(shù): 8/48頁
文件大?。?/td> 0K
描述: IC UART SINGLE W/FIFO 48-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 250
通道數(shù): 1,UART
FIFO's: 32 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應(yīng)商設(shè)備封裝: 48-LQFP(7x7)
包裝: 管件
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
16 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.
Register descriptions
Table 8 details the assigned bit functions for the seventeen SC16C650B internal registers.
The assigned bit functions are more fully dened in Section 7.1 through Section 7.11.
[1]
The value shown represents the register’s initialized HEX value; X = n/a.
[2]
These registers are accessible only when LCR[7] = 0.
[3]
These bits are only accessible when EFR[4] is set.
[4]
This function is not supported in the HVQFN32 package, and should not be written.
[5]
OUT2 pin is not supported in the HVQFN32 package, and this bit should not be written.
Table 8.
SC16C650B internal registers
A2
A1
A0
Register Default
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General register set[2]
0
RHR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
THR
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
IER
00
CTS
interrupt
RTS
interrupt
Xoff
interrupt
Sleep
mode[3]
modem
status
interrupt
receive
line status
interrupt
transmit
holding
register
receive
holding
register
0
1
0
FCR
00
RCVR
trigger
(MSB)
RCVR
trigger
(LSB)
TX
trigger
(MSB)[3]
TX
trigger
(LSB)[3]
DMA mode
select[4]
XMIT
FIFO
reset
RCVR
FIFO
reset
FIFO
enable
0
1
0
ISR
01
FIFOs
enabled
FIFOs
enabled
INT
priority
bit 4
INT
priority
bit 3
INT priority
bit 2
INT
priority
bit 1
INT
priority
bit 0
INT
status
0
1
LCR
00
divisor
latch
enable
set
break
set parity even
parity
enable
stop bits
word
length
bit 1
word
length
bit 0
1
0
MCR
00
Clock
select[3]
IR
enable[3]
INT type
select[3]
loopback
OUT2[5]
OUT1,
RTS
DTR
1
0
1
LSR
60
FIFO
data
error
trans.
empty
trans.
holding
empty
break
interrupt
framing
error
parity
error
overrun
error
receive
data
ready
1
0
MSR
X0
DCD
RI
DSR
CTS
DCD
RI
DSR
CTS
1
SPR
FF
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
Special register set[7]
0
DLL
XX
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
0
1
DLM
XX
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
Enhanced register set[8]
0
1
0
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
IER[4:7],
ISR[4,5],
FCR[4,5],
MCR[5:7]
Cont-3
Tx, Rx
control
Cont-2
Tx, Rx
control
Cont-1
Tx, Rx
control
Cont-0
Tx, Rx
control
1
0
Xon1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
0
1
Xon2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
1
0
Xoff1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
1
Xoff2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
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