參數(shù)資料
型號: SC16C650BIBS
廠商: NXP Semiconductors N.V.
元件分類: 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C650BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C650BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁數(shù): 16/48頁
文件大小: 241K
代理商: SC16C650BIBS
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
16 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
7.
Register descriptions
Table 8
details the assigned bit functions for the seventeen SC16C650B internal registers.
The assigned bit functions are more fully defined in
Section 7.1
through
Section 7.11
.
[1]
The value shown represents the register’s initialized HEX value; X = n/a.
[2]
These registers are accessible only when LCR[7] = 0.
[3]
These bits are only accessible when EFR[4] is set.
[4]
This function is not supported in the HVQFN32 package, and should not be written.
[5]
OUT2 pin is not supported in the HVQFN32 package, and this bit should not be written.
Table 8.
A2
SC16C650B internal registers
A0
Register Default
[1]
A1
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
General register set
[2]
0
0
0
0
0
0
0
0
1
RHR
THR
IER
XX
XX
00
bit 7
bit 7
CTS
interrupt
[3]
bit 6
bit 6
RTS
interrupt
[3]
bit 5
bit 5
Xoff
interrupt
[3]
bit 4
bit 4
Sleep
mode
[3]
bit 3
bit 3
modem
status
interrupt
DMAmode
select
[4]
bit 2
bit 2
receive
linestatus
interrupt
XMIT
FIFO
reset
INT
priority
bit 1
stop bits
bit 1
bit 1
transmit
holding
register
RCVR
FIFO
reset
INT
priority
bit 0
word
length
bit 1
RTS
bit 0
bit 0
receive
holding
register
FIFO
enable
0
1
0
FCR
00
RCVR
trigger
(MSB)
FIFOs
enabled
RCVR
trigger
(LSB)
FIFOs
enabled
TX
trigger
(MSB)
[3]
INT
priority
bit 4
set parity even
TX
trigger
(LSB)
[3]
INT
priority
bit 3
0
1
0
ISR
01
INT priority
bit 2
INT
status
0
1
1
LCR
00
divisor
latch
enable
Clock
select
[3]
FIFO
data
error
DCD
bit 7
set
break
parity
parity
enable
word
length
bit 0
DTR
1
0
0
MCR
00
IR
enable
[3]
trans.
empty
INT type
select
[3]
trans.
holding
empty
DSR
bit 5
loopback
OUT2
[5]
OUT1,
OUT
[6]
parity
error
1
0
1
LSR
60
break
interrupt
framing
error
overrun
error
receive
data
ready
CTS
bit 0
1
1
Special register set
[7]
0
0
0
0
0
1
Enhanced register set
[8]
0
1
0
1
1
0
1
MSR
SPR
X0
FF
RI
bit 6
CTS
bit 4
DCD
bit 3
RI
bit 2
DSR
bit 1
DLL
DLM
XX
XX
bit 7
bit 15
bit 6
bit 14
bit 5
bit 13
bit 4
bit 12
bit 3
bit 11
bit 2
bit 10
bit 1
bit 9
bit 0
bit 8
EFR
00
Auto
CTS
Auto
RTS
Special
char.
select
Enable
IER[4:7],
ISR[4,5],
FCR[4,5],
MCR[5:7]
bit 4
bit 12
bit 4
bit 12
Cont-3
Tx, Rx
control
Cont-2
Tx, Rx
control
Cont-1
Tx, Rx
control
Cont-0
Tx, Rx
control
1
1
1
1
0
0
1
1
0
1
0
1
Xon1
Xon2
Xoff1
Xoff2
00
00
00
00
bit 7
bit 15
bit 7
bit 15
bit 6
bit 14
bit 6
bit 14
bit 5
bit 13
bit 5
bit 13
bit 3
bit 11
bit 3
bit 11
bit 2
bit 10
bit 2
bit 10
bit 1
bit 9
bit 1
bit 9
bit 0
bit 8
bit 0
bit 8
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