參數(shù)資料
型號(hào): SC16C650BIBS
廠商: NXP Semiconductors N.V.
元件分類(lèi): 收發(fā)器
英文描述: 5 V, 3.3 V and 2.5 V UART with 32-byte FIFOs and infrared (IrDA) encoder-decoder
封裝: SC16C650BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html<1<Always Pb-free,;SC16C650BIB48<SOT313-2 (LQFP48)|<<http://www.nxp.com/packages/SOT313-2.html&
文件頁(yè)數(shù): 8/48頁(yè)
文件大小: 241K
代理商: SC16C650BIBS
SC16C650B_4
NXP B.V. 2009. All rights reserved.
Product data sheet
Rev. 04 — 14 September 2009
8 of 48
NXP Semiconductors
SC16C650B
UART with 32-byte FIFOs and IrDA encoder/decoder
[1]
HVQFN32 package die supply ground is connected to both GND pin and exposed center pad. GND pin must be connected to supply
ground for proper device operation. For enhanced thermal, electrical, and board level performance, the exposed pad needs to be
soldered to the board using a corresponding thermal pad on the board and for proper heat conduction through the board, thermal vias
need to be incorporated in the PCB in the thermal pad region.
[2]
In Sleep mode, XTAL2 is left floating.
6.
Functional description
The SC16C650B provides serial asynchronous receive data synchronization,
parallel-to-serial and serial-to-parallel data conversions for both the transmitter and
receiver sections. These functions are necessary for converting the serial data stream into
parallel data that is required with digital data systems. Synchronization for the serial data
stream is accomplished by adding start and stop bits to the transmit data to form a data
character (character orientated protocol). Data integrity is insured by attaching a parity bit
to the data character. The parity bit is checked by the receiver for any transmission bit
errors. The SC16C650B is fabricated with an advanced CMOS process to achieve low
drain power and high speed requirements.
The SC16C650B is an upward solution that provides 32 bytes of transmit and receive
FIFO memory, instead of none in the 16C450, or 16 bytes in the 16C550. The
SC16C650B is designed to work with high speed modems and shared network
environments that require fast data processing time. Increased performance is realized in
the SC16C650B by the larger transmit and receive FIFOs. This allows the external
processor to handle more networking tasks within a given time. In addition, the four
selectable levels of FIFO trigger interrupt and automatic hardware/software flow control is
uniquely provided for maximum data throughput performance, especially when operating
in a multi-channel environment. The combination of the above greatly reduces the
bandwidth requirement of the external controlling CPU, increases performance, and
reduces power consumption.
The SC16C650B is capable of operation up to 3 Mbit/s with a 48 MHz external clock input
(at 5 V).
The rich feature set of the SC16C650B is available through internal registers. Automatic
hardware/software flow control, selectable transmit and receive FIFO trigger level,
selectable TX and RX baud rates, modem interface controls, and a Sleep mode are some
of these features.
XTAL1
XTAL2
[2]
18
19
14
15
9
10
I
O
Crystal connection or external clock input.
Crystal connection or the inversion of XTAL1 if XTAL1 is
driven.
not connected
n.c.
1,12,23,
34
1, 6, 13,
21, 25,
36, 37,
48
12
-
Table 2.
Symbol
Pin description
…continued
Pin
PLCC44
LQFP48 HVQFN32
Type
Description
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SC16C650BIBS-S 功能描述:UART 接口集成電路 16CB 2.5V-5V 1CH UART 32B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel