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參數(shù)資料
型號: SC16C654DBIB64,151
廠商: NXP Semiconductors
文件頁數(shù): 25/58頁
文件大?。?/td> 0K
描述: IC UART QUAD W/FIFO 64-LQFP
產(chǎn)品培訓模塊: Stand-Alone UARTs
標準包裝: 160
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶IrDA 編碼器/解碼器:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(10x10)
包裝: 托盤
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-2048
935276671151
SC16C654DBIB64-S
31
7674F–AVR–09/09
ATmega164P/324P/644P
7.2.2
Clock Startup Sequence
Any clock source needs a sufficient V
CC to start oscillating and a minimum number of oscillating
cycles before it can be considered stable.
To ensure sufficient V
CC, the device issues an internal reset with a time-out delay (tTOUT) after
the device reset is released by all other reset sources. “On-chip Debug System” on page 45
describes the start conditions for the internal reset. The delay (t
TOUT) is timed from the Watchdog
Oscillator and the number of cycles in the delay is set by the SUTx and CKSELx fuse bits. The
selectable delays are shown in Table 7-2. The frequency of the Watchdog Oscillator is voltage
Main purpose of the delay is to keep the AVR in reset until it is supplied with minimum Vcc. The
delay will not monitor the actual voltage and it will be required to select a delay longer than the
Vcc rise time. If this is not possible, an internal or external Brown-Out Detection circuit should be
used. A BOD circuit will ensure sufficient Vcc before it releases the reset, and the time-out delay
can be disabled. Disabling the time-out delay without utilizing a Brown-Out Detection circuit is
not recommended.
The oscillator is required to oscillate for a minimum number of cycles before the clock is consid-
ered stable. An internal ripple counter monitors the oscillator output clock, and keeps the internal
reset active for a given number of clock cycles. The reset is then released and the device will
start to execute. The recommended oscillator start-up time is dependent on the clock type, and
varies from 6 cycles for an externally applied clock to 32K cycles for a low frequency crystal.
The start-up sequence for the clock includes both the time-out delay and the start-up time when
the device starts up from reset. When starting up from Power-save or Power-down mode, Vcc is
assumed to be at a sufficient level and only the start-up time is included.
7.2.3
Clock Source Connections
The pins XTAL1 and XTAL2 are input and output, respectively, of an inverting amplifier which
can be configured for use as an On-chip Oscillator, as shown in Figure 7-2 on page 32. Either a
quartz crystal or a ceramic resonator may be used.
C1 and C2 should always be equal for both crystals and resonators. The optimal value of the
capacitors depends on the crystal or resonator in use, the amount of stray capacitance, and the
electromagnetic noise of the environment. For ceramic resonators, the capacitor values given by
the manufacturer should be used.
Table 7-2.
Number of Watchdog Oscillator Cycles
Typ Time-out (V
CC = 5.0V)
Typ Time-out (V
CC = 3.0V)
Number of Cycles
0 ms
0
4.1 ms
4.3 ms
512
65 ms
69 ms
8K (8,192)
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SC16C654DIB64 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad UART with 64-byte FIFO and infrared (IrDA) encoder/decoder
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SC16C654DIB64,151 功能描述:UART 接口集成電路 16C 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel
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