參數(shù)資料
型號: SC16C750BIB64,157
廠商: NXP Semiconductors
文件頁數(shù): 13/44頁
文件大?。?/td> 0K
描述: IC UART 64BYTE 64LQFP
標準包裝: 800
通道數(shù): 1,UART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應商設備封裝: 64-LQFP(10x10)
包裝: 托盤
其它名稱: 935274403157
SC16C750BIB64
SC16C750BIB64-ND
SC16C750B_5
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 05 — 17 October 2008
20 of 44
NXP Semiconductors
SC16C750B
5 V, 3.3 V and 2.5 V UART with 64-byte FIFOs
7.4 Interrupt Status Register (ISR)
The SC16C750B provides four levels of prioritized interrupts to minimize external software
interaction. The Interrupt Status Register (ISR) provides the user with four interrupt status
bits. Performing a read cycle on the ISR will provide the user with the highest pending
interrupt level to be serviced. No other interrupts are acknowledged until the pending
interrupt is serviced. Whenever the interrupt status register is read, the interrupt status is
cleared. However, it should be noted that only the current pending interrupt is cleared by
the read. A lower level interrupt may be seen after re-reading the interrupt status bits.
Table 12 “Interrupt source” shows the data values (bit 0 to bit 4) for the four prioritized
interrupt levels and the interrupt sources associated with each of these interrupt levels.
Table 12.
Interrupt source
Priority
level
ISR[3]
ISR[2]
ISR[1]
ISR[0]
Source of the interrupt
1
0
1
0
LSR (Receiver Line Status Register)
2
0
1
0
RXRDY (Received Data Ready)
2
1
0
RXRDY (Receive Data time-out)
3
0
1
0
TXRDY (Transmitter Holding Register Empty)
4
0
MSR (Modem Status Register)
Table 13.
Interrupt Status Register bits description
Bit
Symbol
Description
7:6
ISR[7:6]
FIFOs enabled. These bits are set to a logic 0 when the FIFO is not
being used. They are set to a logic 1 when the FIFOs are enabled.
logic 0 or cleared = default condition
5
ISR[5]
64-byte FIFO enable.
logic 0 = 16-byte operation
logic 1 = 64-byte operation
4
ISR[4]
not used
3:1
ISR[3:1]
INT priority bit 2 to bit 0. These bits indicate the source for a pending
interrupt at interrupt priority levels 1, 2, and 3 (see Table 12).
logic 0 or cleared = default condition
0
ISR[0]
INT status.
logic 0 = an interrupt is pending and the ISR contents may be used
as a pointer to the appropriate interrupt service routine
logic 1 = no interrupt pending (normal default condition)
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