參數(shù)資料
型號: SC16C752BIB48,151
廠商: NXP Semiconductors
文件頁數(shù): 5/47頁
文件大小: 0K
描述: IC DUAL UART 64BYTE 48LQFP
標準包裝: 250
通道數(shù): 2,DUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調制解調器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 48-LQFP
供應商設備封裝: 48-LQFP(7x7)
包裝: 托盤
其它名稱: 935274411151
SC16C752BIB48-S
SC16C752BIB48-S-ND
SC16C752B
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2010. All rights reserved.
Product data sheet
Rev. 6 — 30 November 2010
13 of 47
NXP Semiconductors
SC16C752B
5 V, 2.2 V and 2.5 V dual UART, 5 Mbit/s (max.), with 64-byte FIFOs
6.5 Interrupts
The SC16C752B has interrupt generation and prioritization (six prioritized levels of
interrupts) capability. The Interrupt Enable Register (IER) enables each of the six types of
interrupts and the INTA/INTB signal in response to an interrupt generation. The IER can
also disable the interrupt system by clearing bit 0 to bit 3 and bit 5 to bit 7. When an
interrupt is generated, the IIR indicates that an interrupt is pending and provides the type
of interrupt through IIR[5:0]. Table 6 summarizes the interrupt control functions.
It is important to note that for the framing error, parity error, and break conditions, LSR[7]
generates the interrupt. LSR[7] is set when there is an error anywhere in the RX FIFO,
and is cleared only when there are no more errors remaining in the FIFO. LSR[4:2] always
represent the error status for the received character at the top of the RX FIFO. Reading
the RX FIFO updates LSR[4:2] to the appropriate status for the new character at the top of
the FIFO. If the RX FIFO is empty, then LSR[4:2] are all zeros.
For the Xoff interrupt, if an Xoff flow character detection caused the interrupt, the interrupt
is cleared by an Xon flow character detection. If a special character detection caused the
interrupt, the interrupt is cleared by a read of the LSR.
Table 6.
Interrupt control functions
IIR[5:0]
Priority
level
Interrupt type
Interrupt source
Interrupt reset method
00 0001
None
none
00 0110
1
receiver line status
OE, FE, PE, or BI errors occur in
characters in the RX FIFO
FE, PE, BI: all erroneous
characters are read from the
RX FIFO.
OE: read LSR
00 1100
2
RX time-out
stale data in RX FIFO
read RHR
00 0100
2
RHR interrupt
DRDY (data ready)
(FIFO disable)
RX FIFO above trigger level
(FIFO enable)
read RHR
00 0010
3
THR interrupt
TFE (THR empty)
(FIFO disable)
TX FIFO passes above trigger level
(FIFO enable)
read IIR or a write to the THR
00 0000
4
modem status
MSR[3:0] = logic 0
read MSR
01 0000
5
Xoff interrupt
receive Xoff character(s)/special
character
receive Xon character(s)/Read of
IIR
10 0000
6
CTS, RTS
RTSn pin or CTSn pin change state
from active (LOW) to inactive (HIGH)
read IIR
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