參數(shù)資料
型號： SC16C752IB48,151
廠商： NXP Semiconductors
文件頁數(shù)： 8/47頁
文件大小： 0K
描述： IC UART DUAL W/FIFO 48-LQFP
標準包裝： 250
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
電源電壓： 2.5V，3.3V，5V
帶自動流量控制功能： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 48-LQFP
供應(yīng)商設(shè)備封裝： 48-LQFP（7x7）
包裝： 托盤
其它名稱： 568-3289
935270055151
SC16C752IB48-S
Philips Semiconductors
SC16C752
Dual UART with 64-byte FIFO
Product data
Rev. 04 — 20 June 2003
16 of 47
9397 750 11635
Koninklijke Philips Electronics N.V. 2003. All rights reserved.
6.8 Break and time-out conditions
An RX idle condition is detected when the receiver line, RX, has been HIGH for
4 character time. The receiver line is sampled midway through each bit.
When a break condition occurs, the TX line is pulled LOW. A break condition is
activated by setting LCR[6].
6.9 Programmable baud rate generator
The SC16C752 UART contains a programmable baud generator that takes any clock
input and divides it by a divisor in the range between 1 and (216
1). An additional
divide-by-4 prescaler is also available and can be selected by MCR[7], as shown in
Figure 11. The output frequency of the baud rate generator is 16
× the baud rate. The
formula for the divisor is:
Where:
prescaler = 1, when MCR[7] is set to 0 after reset (divide-by-1 clock selected)
prescaler = 4, when MCR[7] is set to 1 after reset (divide-by-4 clock selected).
Remark: The default value of prescaler after reset is divide-by-1.
Figure 11 shows the internal prescaler and baud rate generator circuitry.
DLL and DLH must be written to in order to program the baud rate. DLL and DLH are
the least signicant and most signicant byte of the baud rate divisor. If DLL and DLH
are both zero, the UART is effectively disabled, as no baud clock will be generated.
Remark: The programmable baud rate generator is provided to select both the
transmit and receive clock rates.
Table 7 and Table 8 show the baud rate and divisor correlation for crystal with
frequency 1.8432 MHz and 3.072 MHz, respectively.
Figure 12 shows the crystal clock circuit reference.
Fig 11. Prescaler and baud rate generator block diagram.
divisor
XTAL1 crystal input frequency
prescaler
---------------------------------------------------------------------------
desired baud rate
16
×
()
---------------------------------------------------------------------------------
=
BAUD RATE
GENERATOR
LOGIC
MCR[7] = 1
MCR[7] = 0
PRESCALER
LOGIC
(DIVIDE-BY-1)
INTERNAL
OSCILLATOR
LOGIC
002aaa233
XTAL1
XTAL2
INPUT CLOCK
PRESCALER
LOGIC
(DIVIDE-BY-4)
REFERENCE
CLOCK
INTERNAL
BAUD RATE
CLOCK FOR
TRANSMITTER
AND
RECEIVER
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