參數(shù)資料
型號: SC16C754BIB80,528
廠商: NXP Semiconductors
文件頁數(shù): 22/50頁
文件大?。?/td> 0K
描述: IC UART QUAD 64BYTE 80LQFP
標準包裝: 1,000
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 80-LQFP
供應商設備封裝: 80-LQFP(12x12)
包裝: 帶卷 (TR)
其它名稱: 935274939528
SC16C754BIB80-T
SC16C754BIB80-T-ND
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
29 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.8 Interrupt Enable Register (IER)
The Interrupt Enable Register (IER) enables each of the six types of interrupt, receiver
error, RHR interrupt, THR interrupt, Xoff received, or CTS/RTS change of state from LOW
to HIGH. The INT output signal is activated in response to interrupt generation. Table 16
shows the interrupt enable register bit settings.
[1]
IER[7:4] can only be modied if EFR[4] is set, that is, EFR[4] is a write enable. Re-enabling IER[1] will
cause a new interrupt if the THR is below the threshold.
Table 16.
Interrupt enable register bits description
Bit
Symbol
Description
7
CTS interrupt enable.
logic 0 = disable the CTS interrupt (normal default condition)
logic 1 = enable the CTS interrupt
6
RTS interrupt enable.
logic 0 = disable the RTS interrupt (normal default condition)
logic 1 = enable the RTS interrupt
5
Xoff interrupt.
logic 0 = disable the Xoff interrupt (normal default condition)
logic 1 = enable the Xoff interrupt
4
Sleep mode.
logic 0 = disable Sleep mode (normal default condition)
logic 1 = enable Sleep mode. See Section 6.7 “Sleep mode” for details.
3
IER[3]
Modem status interrupt.
logic 0 = disable the modem status register interrupt (normal default
condition)
logic 1 = enable the modem status register interrupt
2
IER[2]
Receive line status interrupt.
logic 0 = disable the receiver line status interrupt (normal default condition)
logic 1 = enable the receiver line status interrupt
1
IER[1]
Transmit holding register interrupt.
logic 0 = disable the THR interrupt (normal default condition)
logic 1 = enable the THR interrupt
0
IER[0]
Receive holding register interrupt.
logic 0 = disable the RHR interrupt (normal default condition)
logic 1 = enable the RHR interrupt
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