參數(shù)資料
型號: SC16C754BIBM,151
廠商: NXP Semiconductors
文件頁數(shù): 20/50頁
文件大小: 0K
描述: IC UART QUAD W/FIFO 64-LQFP
產(chǎn)品培訓(xùn)模塊: Stand-Alone UARTs
標(biāo)準(zhǔn)包裝: 250
通道數(shù): 4,QUART
FIFO's: 64 字節(jié)
電源電壓: 2.5V,3.3V,5V
帶自動(dòng)流量控制功能:
帶故障啟動(dòng)位檢測功能:
帶調(diào)制解調(diào)器控制功能:
安裝類型: 表面貼裝
封裝/外殼: 64-LQFP
供應(yīng)商設(shè)備封裝: 64-LQFP(7x7)
包裝: 托盤
產(chǎn)品目錄頁面: 828 (CN2011-ZH PDF)
其它名稱: 568-3290
935279069151
SC16C754BIBM-S
SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
27 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
7.6 Modem Control Register (MCR)
The MCR controls the interface with the modem, data set, or peripheral device that is
emulating the modem. Table 14 shows modem control register bit settings.
[1]
MCR[7:5] can only be modied when EFR[4] is set, that is, EFR[4] is a write enable.
Table 14.
Modem control register bits description
Bit
Symbol
Description
7
MCR[7][1]
Clock select.
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6
MCR[6][1]
TCR and TLR enable.
logic 0 = no action
logic 1 = enable access to the TCR and TLR registers
5
MCR[5][1]
Xon Any.
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
4
MCR[4]
Enable loopback.
logic 0 = normal operating mode
logic 1 = enable local loopback mode (internal). In this mode the
MCR[3:0] signals are looped back into MSR[7:4] and the TX output is
looped back to the RX input internally.
3
MCR[3]
IRQ enable OP.
logic 0 = forces INTA to INTD outputs to the 3-state mode and OP
output to HIGH state
logic 1 = forces the INTA to INTD outputs to the active state and OP
output to LOW state. In loopback mode, controls MSR[7].
2
MCR[2]
FIFO Ready enable.
logic 0 = disable the FIFO Rdy register
logic 1 = enable the FIFO Rdy register. In loopback mode, controls
MSR[6].
1
MCR[1]
RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW). In loopback mode, controls
MSR[4]. If auto-RTS is enabled, the RTS output is controlled by
hardware ow control.
0
MCR[0]
DTR
logic 0 = force DTR output to inactive (HIGH)
logic 1 = force DTR output to active (LOW). In loopback mode, controls
MSR[5].
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