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參數(shù)資料
| 型號(hào)： | SC16C754BIBM,151 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 48/50頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART QUAD W/FIFO 64-LQFP |
| 產(chǎn)品培訓(xùn)模塊： | Stand-Alone UARTs |
| 標(biāo)準(zhǔn)包裝： | 250 |
| 通道數(shù)： | 4，QUART |
| FIFO's： | 64 字節(jié) |
| 電源電壓： | 2.5V，3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶故障啟動(dòng)位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-LQFP |
| 供應(yīng)商設(shè)備封裝： | 64-LQFP（7x7） |
| 包裝： | 托盤 |
| 產(chǎn)品目錄頁面： | 828 (CN2011-ZH PDF) |
| 其它名稱： | 568-3290 935279069151 SC16C754BIBM-S |
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SC16C754B_4
NXP B.V. 2008. All rights reserved.
Product data sheet
Rev. 04 — 6 October 2008
7 of 51
NXP Semiconductors
SC16C754B
5 V, 3.3 V and 2.5 V quad UART, 5 Mbit/s (max.) with 64-byte FIFOs
CSA
7
9
16
I
Chip Select (active LOW). These pins enable data transfers between
the user CPU and the SC16C754B for the channel(s) addressed.
Individual UART sections (A, B, C, D) are addressed by providing a logic
LOW on the respective CSA through CSD pins.
CSB
11
13
20
CSC
38
49
50
CSD
42
53
54
CTSA
2
4
11
I
Clear to Send (active LOW). These inputs are associated with individual
UART channels A through D. A logic 0 (LOW) on the CTS pins indicates
the modem or data set is ready to accept transmit data from the
SC16C754B. Status can be tested by reading MSR[4]. These pins only
affect the transmit and receive operations when auto-CTS function is
enabled via the Enhanced Feature Register EFR[7] for hardware ow
control operation.
CTSB
16
18
25
CTSC
33
44
45
CTSD
47
58
59
D0 to D7
53, 54,
55, 56,
57, 58,
59, 60
68, 69,
70, 71,
72, 73,
74, 75
66, 67,
68, 1, 2,
3, 4, 5
I/O
Data bus (bidirectional). These pins are the 8-bit, 3-state data bus for
transferring information to or from the controlling CPU. D0 is the least
signicant bit and the rst data bit in a transmit or receive serial data
stream.
DSRA
1
3
10
I
Data Set Ready (active LOW). These inputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates the modem or data set is powered-on and is ready for data
exchange with the UART. The state of these inputs is reected in the
Modem Status Register (MSR).
DSRB
17
19
26
DSRC
32
43
44
DSRD
48
59
60
DTRA
3
5
12
O
Data Terminal Ready (active LOW). These outputs are associated with
individual UART channels A through D. A logic 0 (LOW) on these pins
indicates that the SC16C754B is powered-on and ready. These pins can
be controlled via the Modem Control Register (MCR). Writing a logic 1 to
MCR[0] will set the DTR output to logic 0 (LOW), enabling the modem.
The output of these pins will be a logic 1 after writing a logic 0 to MCR[0],
or after a reset.
DTRB
15
17
24
DTRC
34
45
46
DTRD
46
57
58
GND
14, 28,
45, 61
16, 36,
56, 76
6, 23,
40, 57
I
Signal and power ground.
INTA
6
8
15
O
Interrupt A, B, C, and D (active HIGH). These pins provide individual
channel interrupts INTA through INTD. INTA through INTD are enabled
when MCR[3] is set to a logic 1, interrupt sources are enabled in the
Interrupt Enable Register (IER). Interrupt conditions include: receiver
errors, available receiver buffer data, available transmit buffer space, or
when a modem status ag is detected. INTA to INTD are in the
high-impedance state after reset.
INTB
12
14
21
INTC
37
48
49
INTD
43
54
55
INTSEL
-
67
65
I
Interrupt Select (active HIGH with internal pull-down). INTSEL can be
used in conjunction with MCR[3] to enable or disable the 3-state
interrupts INTA to INTD or override MCR[3] and force continuous
interrupts. Interrupt outputs are enabled continuously by making this pin a
logic 1. Driving this pin LOW allows MCR[3] to control the 3-state
interrupt output. In this mode, MCR[3] is set to a logic 1 to enable the
3-state outputs. This pin is associated with LQFP80 and PLCC68
packages only. This pin is connected to GND internally on the LQFP64
package.
IOR
40
51
52
I
Input/Output Read strobe (active LOW). A HIGH-to-LOW transition on
IOR will load the contents of an internal register dened by address bits
A[2:0] onto the SC16C754B data bus (D[7:0]) for access by external
CPU.
Table 2.
Pin description …continued
Symbol
Pin
Type
Description
LQFP64 LQFP80 PLCC68
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC16C754BIBM-F | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754BIBM-S | 功能描述:UART 接口集成電路 16CB 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754IA68 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Quad UART with 64-byte FIFO |
| SC16C754IA68,512 | 功能描述:UART 接口集成電路 16C 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC16C754IA68,518 | 功能描述:UART 接口集成電路 16C 2.5V-5V 4CH UART 64B FIFO RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
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