參數(shù)資料
型號： SC16C852VIET,157
廠商： NXP Semiconductors
文件頁數(shù)： 15/55頁
文件大小： 0K
描述： IC UART DUAL W/FIFO 36TFBGA
產品培訓模塊： Stand-Alone UARTs
標準包裝： 2,450
特點： 可編程
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調制解調器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應商設備封裝： 36-TFBGA（3.5x3.5）
包裝： 托盤
其它名稱： 568-4019
935282518157
SC16C852VIET
SC16C852VIET-ND
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SC1
6
C852
V
A
lli
n
for
m
at
ion
pr
ovi
ded
in
this
do
cum
ent
i
s
sub
jec
tto
leg
a
ld
is
c
la
im
er
s.
NXP
B
.V
.201
1.
Al
lr
ig
h
ts
re
s
e
rv
ed.
Produ
ct
d
a
ta
sheet
Rev
.5
—
21
Jan
uary
201
1
22
o
f55
N
X
P
Semi
conductor
s
SC16C852V
D
u
al
UART
with
128-byte
FIFOs,
IrDA,
and
XScale
VLIO
bus
interface
[1]
The value shown in represents the register’s initialized hexadecimal value; X = not applicable.
[2]
Accessible only when LCR[7] is logic 0, and EFCR[2:1] are logic 0.
[3]
This bit is only accessible when EFR[4] is set.
[4]
Baud rate registers accessible only when LCR[7] is logic 1.
[5]
Second special registers are accessible only when EFCR[0] = 1, and EFCR[2:1] are logic 0.
[6]
Enhanced Feature Register, Xon-1/Xon-2 and Xoff-1/Xoff-2 are accessible only when LCR is set to 0xBF, and EFCR[2:1] are logic0.
[7]
First extra register set is only accessible when EFCR[2:1] = 01b.
[8]
Second extra register set is only accessible when EFCR[2:1] = 10b.
Enhanced register set[6]
0
1
0
EFR
00
Auto CTS
Auto RTS
special
character
select
Enable
IER[7:4],
ISR[5:4],
FCR[5:4],
MCR[7:5]
Cont-3 Tx,
Rx Control
Cont-2 Tx,
Rx Control
Cont-1 Tx,
Rx Control
Cont-0 Tx,
Rx Control
R/W
1
0
Xon-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
1
Xon-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
1
0
Xoff-1
00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
Xoff-2
00
bit 15
bit 14
bit 13
bit 12
bit 11
bit 10
bit 9
bit 8
R/W
First extra register set[7]
0
1
0
TXINTLVL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
RXINTLVL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
FLWCNTH
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
FLWCNTL
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
Second extra register set[8]
0
1
0
CLKPRES
reserved
bit 3
bit 2
bit 1
bit 0
R/W
1
0
RS485TIME
0x00
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
R/W
1
0
AFCR2
0x00
reserved
RS485
RTS invert
Auto
RS485
RTS
RS485
RTS/DTR
transmitter
disable
receiver
disable
9-bit enable
R/W
1
AFCR1
0x00
concurrent
write
reserved
sleep RX
LOW
reserved
RTS/CTS
mapped to
DTR/DSR
software
reset
TSR
interrupt
R/W
Table 9.
SC16C852V internal registers …continued
A3
A2
A1
Register
Default[1]
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
R/W
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