參數(shù)資料
型號： SC16C852VIET,157
廠商： NXP Semiconductors
文件頁數(shù)： 2/55頁
文件大?。?/td> 0K
描述： IC UART DUAL W/FIFO 36TFBGA
產(chǎn)品培訓(xùn)模塊： Stand-Alone UARTs
標(biāo)準(zhǔn)包裝： 2,450
特點(diǎn)： 可編程
通道數(shù)： 2，DUART
FIFO's： 128 字節(jié)
規(guī)程： RS485
電源電壓： 2.5V
帶自動流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動位檢測功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 36-TFBGA
供應(yīng)商設(shè)備封裝： 36-TFBGA（3.5x3.5）
包裝： 托盤
其它名稱： 568-4019
935282518157
SC16C852VIET
SC16C852VIET-ND
SC16C852V
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 5 — 21 January 2011
10 of 55
NXP Semiconductors
SC16C852V
Dual UART with 128-byte FIFOs, IrDA, and XScale VLIO bus interface
6.2 Extended mode (128-byte FIFO)
The device is in the extended mode when any of these four registers contains any value
other than 0: FLWCNTH, FLWCNTL, TXINTLVL, RXINTLVL.
6.3 Internal registers
The SC16C852V provides two sets of internal registers (A and B) consisting of
25 registers each for monitoring and controlling the functions of each channel of the
UART. These registers are shown in Table 4.
[1]
These registers are accessible only when LCR[7] is a logic 0.
Table 4.
Internal registers decoding
A3
A2
A1
Read mode
Write mode
General register set (THR/RHR, IER/ISR, MCR/MSR, FCR, LCR, LSR, EFCR, SPR)[1]
000Receive Holding Register
Transmit Holding Register
001Interrupt Enable Register
Interrupt Enable Register
010Interrupt Status Register
FIFO Control Register
011Line Control Register
Line Control Register
100Modem Control Register
Modem Control Register
101Line Status Register
Extra Feature Control Register (EFCR)
110Modem Status Register
n/a
111Scratchpad Register
Scratchpad Register
Baud rate register set (DLL/DLM)[2]
000LSB of Divisor Latch
LSB of Divisor Latch
001MSB of Divisor Latch
MSB of Divisor Latch
Second special register set (TXLVLCNT/RXLVLCNT)[3]
011Transmit FIFO Level Count
n/a
100Receive FIFO Level Count
n/a
Enhanced register set (EFR, Xon1/Xon2, Xoff1/Xoff2)[4]
010Enhanced Feature Register
Enhanced Feature Register
100Xon1 word
Xon1 word
101Xon2 word
Xon2 word
110Xoff1 word
Xoff1 word
111Xoff2 word
Xoff2 word
First extra feature register set (TXINTLVL/RXINTLVL, FLWCNTH/FLWCNTL)[5]
010Transmit FIFO Interrupt Level
Transmit FIFO Interrupt Level
100Receive FIFO Interrupt Level
Receive FIFO Interrupt Level
110Flow Control Count High
Flow Control Count High
111Flow Control Count Low
Flow Control Count Low
Second extra feature register set (CLKPRES, RS485TIME, AFCR2, AFCR1)[6]
0
1
0
Clock Prescaler
100RS-485 turn-around Timer
RS-485 turn-around Timer
110Additional Feature Control Register 2
Additional Feature Control Register 2
111Additional Feature Control Register 1
Additional Feature Control Register 1
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