參數(shù)資料
型號(hào)： SC16IS752IPW-T
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 19/60頁(yè)
文件大?。?/td> 0K
描述： IC UART DUAL I2C/SPI 28-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
特點(diǎn)： 低電流
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.5V, 3.3V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
配用： 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
26 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.7 Modem Control Register (MCR)
The MCR controls the interface with the mode, data set, or peripheral device that is
emulating the modem. Table 19 shows Modem Control Register bit settings.
[1]
MCR[7:5] and MCR[2] can only be modified when EFR[4] is set, that is, EFR[4] is a write enable.
Table 19.
Modem Control Register bits description
Bit
Symbol
Description
7
Clock divisor.
logic 0 = divide-by-1 clock input
logic 1 = divide-by-4 clock input
6
IrDA mode enable.
logic 0 = normal UART mode
logic 1 = IrDA mode
5
Xon Any.
logic 0 = disable Xon Any function
logic 1 = enable Xon Any function
4
MCR[4]
Enable loopback.
logic 0 = normal operating mode
logic 1 = enable local Loopback mode (internal). In this mode the
MCR[1:0] signals are looped back into MSR[4:5] and the TX output is
looped back to the RX input internally.
3
MCR[3]
reserved
2
MCR[2]
TCR and TLR enable.
logic 0 = disable the TCR and TLR register
logic 1 = enable the TCR and TLR register
1
MCR[1]
RTS
logic 0 = force RTS output to inactive (HIGH)
logic 1 = force RTS output to active (LOW). In Loopback mode,
controls MSR[4]. If Auto-RTS is enabled, the RTS output is controlled
by hardware flow control.
0
MCR[0]
DTR. If GPIO5 or GPIO1 is selected as DTR modem pin through
IOControl register bit 1 or bit 2, the state of DTR pin can be controlled as
below. Writing to IOState bit 5 or bit 1 will not have any effect on the DTR
pin.
logic 0 = force DTR output to inactive (HIGH)
logic 1 = force DTR output to active (LOW)
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