參數(shù)資料
型號(hào)： SC16IS752IPW-T
廠(chǎng)商： NXP Semiconductors
文件頁(yè)數(shù)： 21/60頁(yè)
文件大?。?/td> 0K
描述： IC UART DUAL I2C/SPI 28-TSSOP
標(biāo)準(zhǔn)包裝： 2,500
特點(diǎn)： 低電流
通道數(shù)： 2，DUART
FIFO's： 64 字節(jié)
規(guī)程： RS232，RS485
電源電壓： 2.5V, 3.3V
帶自動(dòng)流量控制功能： 是
帶IrDA 編碼器/解碼器： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
安裝類(lèi)型： 表面貼裝
封裝/外殼： 28-TSSOP（0.173"，4.40mm 寬）
供應(yīng)商設(shè)備封裝： 28-TSSOP
包裝： 帶卷 (TR)
配用： 568-4000-ND - DEMO BOARD SPI/I2C TO DUAL UART
568-3510-ND - DEMO BOARD SPI/I2C TO UART
SC16IS752_SC16IS762
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 9 — 22 March 2012
28 of 60
NXP Semiconductors
SC16IS752; SC16IS762
Dual UART with I2C-bus/SPI interface, 64-byte FIFOs, IrDA SIR
8.9 Modem Status Register (MSR)
This 8-bit register provides information about the current state of the control lines from the
modem, data set, or peripheral device to the host. It also indicates when a control input
from the modem changes state. Table 21 shows Modem Status Register bit settings per
channel.
Remark: The primary inputs RI, CD, CTS, DSR are all active LOW.
8.10 Scratchpad Register (SPR)
The SC16IS752/SC16IS762 provides a temporary data register to store 8 bits of user
information.
Table 21.
Modem Status Register bits description
Bit
Symbol
Description
7
MSR[7]
CD (active HIGH, logical 1). If GPIO6 or GPIO2 is selected as CD
modem pin through IOControl register bit 1 or bit 2, the state of CD pin
can be read from this bit. This bit is the complement of the CD input.
Reading IOState bit 6 or bit 2 does not reflect the true state of CD pin.
6
MSR[6]
RI (active HIGH, logical 1). If GPIO7 or GPIO3 is selected as RI modem
pin through IOControl register bit 1 or bit 2, the state of RI pin can be
read from this bit. This bit is the complement of the RI input. Reading
IOState bit 7 or bit 3 does not reflect the true state of RI pin.
5
MSR[5]
DSR (active HIGH, logical 1). If GPIO4 or GPIO0 is selected as DSR
modem pin through IOControl register bit 1 or bit 2, the state of DSR pin
can be read from this bit. This bit is the complement of the DSR input.
Reading IOState bit 4 or bit 0 does not reflect the true state of DSR pin.
4
MSR[4]
CTS (active HIGH, logical 1). This bit is the complement of the CTS
input.
3MSR[3]
CD. Indicates that CD input has changed state. Cleared on a read.
2MSR[2]
RI. Indicates that RI input has changed state from LOW to HIGH.
Cleared on a read.
1MSR[1]
DSR. Indicates that DSR input has changed state. Cleared on a read.
0MSR[0]
CTS. Indicates that CTS input has changed state. Cleared on a read.
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