參數(shù)資料
型號(hào): SC28L202
廠商: NXP Semiconductors N.V.
英文描述: Dual universal asynchronous receiver/transmitter DUART
中文描述: 雙路通用異步接收器/發(fā)送器杜阿爾特
文件頁數(shù): 66/77頁
文件大?。?/td> 531K
代理商: SC28L202
Philips Semiconductors
Objective specification
SC28L202
Dual UART
2000 Feb 10
60
AC CHARACTERISTICS
1,2,3
(NOMINAL 3.3 VOLTS)
Vcc = 3.3v
±
10% Ta = – 40 to +85 C unless otherwise specified
LIMITS
4
Min
Symbol
Reset timing (See Figure 3)
t
RES
Reset Pulse Width
Bus Timing (See Figure ___)
t
*AS
A6–A0 setup time to RDN, WRN Low
t
*AH
A6–A0 hold time from RDN, WRN low
t
*CS
CEN setup time to RDN, WRN low
t
*CH
CEN Hold time from RDN. WRN Hi
t
*RW
WRN, RDN pulse width (Low time)
t
*DD
Data valid after RDN low (125 pf load) See load table for smaller loads
t
*DA
RDN low to data bus active
t
*DF
Data bus floating after RDN or CEN high
t
*DI
RDN or CEN high to data bus invalid
t
*DS
Data bus setup time before WRN or CEN high (write cycle)
t
*DH
Data hold time after WRN high
t
*RWD
High time between read and/or write cycles
Port Timing (See Figure 7)
t
*PS
Port in setup time before RDN low (Read IP ports cycle)
t
*PH
Port in hold time after RDN high
t
*PD
OP port valid after WRN or CEN high (OPR write cycle)
Interrupt Timing (See Figure 8)
INTRN (or I/O(7:3)B when used as interrupts) negated from:
Read RxFIFO (RxRDY/FFULL interrupt)
Write TxFIFO (TxRDY interrupt)
t
*IR
Reset Command (delta break change interrupt)
Stop C/T command (Counter/timer interrupt
Read IPCR (delta input port change interrupt)
Write IMR (Clear of change interrupt mask bit(s))
Clock Timing (See Figure 9)
t
*CLK
X1/CLK high or low time
f
*CLK
X1/CLK frequency (7.0 to 16.2 MHz with crystal)
f
*CTC
C/T Clk (IP2) high or low time (C/T external clock input)
f
*CTC
C/T Clk (IP2) frequency
t
*RX
RxC high or low time (16X)
f
*RX
RxC Frequency (16X)
RxC Frequency (1x)
t
*TX
TxC High or low time (16X)
f
*TX
TxC frequency (16X)
TxC frequency (1X)
Transmitter Timing (See Figure 12)
t
*TXD
TxD output delay from TxC low (TxC input pin)
t
*TCS
Output delay from TxC output pin low to TxD data output
Receiver Timing (See Figure 13)
t
*RXS
RxD data setup time to RxC high
t
*RXH
RxD data hold time from RxC high
68000 or Motorola bus timing (See Figure ___)
t
DCR
DACKN Low (read cycle) from X1 High
T
DCW
DACKN Low (write cycle) from X1 High
T
DAH
DACKN High from CSN or IACKN high
t
DAT
DACKN High impedance from CSN or IACKN high
t
CSC
CSN or IACKN setup time to X1 high for minimum DACKN cycle
Parameter
Typ
Max
UNIT
100
18
ns
10
25
0
0
20
6
15
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
15
20
50
0
15
25
0
25
0
20
20
–15
14
0
0
–20
–20
50
ns
ns
ns
70
40
40
40
40
40
40
60
60
60
60
60
60
ns
ns
ns
ns
ns
ns
30
1
30
0
30
0
0
30
20
14.7
20
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
34
8
24
1
24
1
0
40
6
60
30
ns
ns
50
50
40
40
ns
ns
18
18
2
10
10
25
25
5
15
ns
ns
ns
ns
15
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