參數(shù)資料
型號: SC28L92A1BS,528
廠商: NXP Semiconductors
文件頁數(shù): 37/73頁
文件大小: 0K
描述: IC UART DUAL W/FIFO 44PQFP
標準包裝: 4,000
系列: IMPACT
特點: 故障啟動位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-HVQFN EP(6x6)
包裝: 帶卷 (TR)
其它名稱: 935281063528
SC28L92A1BS-F
SC28L92A1BS-F-ND
42
2552K–AVR–04/11
ATmega329/3290/649/6490
Figure 10-1. Reset Logic
10.3
Power-on Reset
A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level
is defined in “System and Reset Characteristics” on page 330. The POR is activated whenever
V
CC is below the detection level. The POR circuit can be used to trigger the start-up Reset, as
well as to detect a failure in supply voltage.
A Power-on Reset (POR) circuit ensures that the device is reset from Power-on. Reaching the
Power-on Reset threshold voltage invokes the delay counter, which determines how long the
device is kept in RESET after V
CC rise. The RESET signal is activated again, without any delay,
when V
CC decreases below the detection level.
Figure 10-2. MCU Start-up, RESET Tied to V
CC
MCU Status
Register (MCUSR)
Brown-out
Reset Circuit
BODLEVEL [1..0]
Delay Counters
CKSEL[3:0]
CK
TIMEOUT
WDRF
BORF
EXTRF
PORF
DATA BUS
Clock
Generator
SPIKE
FILTER
Pull-up Resistor
JTRF
JTAG Reset
Register
Watchdog
Oscillator
SUT[1:0]
Power-on Reset
Circuit
V
RESET
TIME-OUT
INTERNAL
RESET
t
TOUT
V
POT
V
RST
CC
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