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參數(shù)資料
| 型號(hào)： | SC28L92A1BS,557 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 11/73頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC UART DUAL W/FIFO 44PQFP |
| 標(biāo)準(zhǔn)包裝： | 2,450 |
| 系列： | IMPACT |
| 特點(diǎn)： | 故障啟動(dòng)位檢測(cè) |
| 通道數(shù)： | 2，DUART |
| FIFO's： | 16 字節(jié) |
| 電源電壓： | 3.3V，5V |
| 帶自動(dòng)流量控制功能： | 是 |
| 帶故障啟動(dòng)位檢測(cè)功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 48-VFQFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 48-HVQFN EP（6x6） |
| 包裝： | 托盤 |
| 其它名稱： | 935281063557 SC28L92A1BS SC28L92A1BS-ND |
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19
2552K–AVR–04/11
ATmega329/3290/649/6490
7.2
SRAM Data Memory
Figure 7-2 shows how the ATmega329/3290/649/6490 SRAM Memory is organized.
The ATmega329/3290/649/6490 is a complex microcontroller with more peripheral units than
can be supported within the 64 locations reserved in the Opcode for the IN and OUT instruc-
tions. For the Extended I/O space from 0x60 - 0xFF in SRAM, only the ST/STS/STD and
LD/LDS/LDD instructions can be used.
The lower 2304/4352 data memory locations address both the Register File, the I/O memory,
Extended I/O memory, and the internal data SRAM. The first 32 locations address the Register
File, the next 64 location the standard I/O memory, then 160 locations of Extended I/O memory,
and the next 2048/4096 locations address the internal data SRAM.
The five different addressing modes for the data memory cover: Direct, Indirect with Displace-
ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register
File, registers R26 to R31 feature the indirect addressing pointer registers.
The direct addressing reaches the entire data space.
The Indirect with Displacement mode reaches 63 address locations from the base address given
by the Y- or Z-register.
When using register indirect addressing modes with automatic pre-decrement and post-incre-
ment, the address registers X, Y, and Z are decremented or incremented.
The 32 general purpose working registers, 64 I/O Registers, 160 Extended I/O Registers, and
the 2,048 bytes of internal data SRAM in the ATmega329/3290/649/6490 are all accessible
through all these addressing modes. The Register File is described in “General Purpose Regis-
Figure 7-2.
Data Memory Map
7.2.1
Data Memory Access Times
This section describes the general access timing concepts for internal memory access. The
internal data SRAM access is performed in two clk
CPU cycles as described in Figure 7-3.
32 Registers
64 I/O Registers
Internal SRAM
(2048 x 8)/
(4096 x 8)
0x0000 - 0x001F
0x0020 - 0x005F
0x08FF/0x10FF
0x0060 - 0x00FF
Data Memory
160 Ext I/O Reg.
0x0100
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| SC28L92A1BS-F | 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28L92A1BS-S | 功能描述:UART 接口集成電路 3V-5V 1CH UART INTEL/MOT INTRF RoHS:否 制造商:Texas Instruments 通道數(shù)量:2 數(shù)據(jù)速率:3 Mbps 電源電壓-最大:3.6 V 電源電壓-最小:2.7 V 電源電流:20 mA 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:LQFP-48 封裝:Reel |
| SC28P-1GREEN | 制造商:Thomas & Betts 功能描述:ID TAG GREEN |
| SC28P-1RED | 制造商:Thomas & Betts 功能描述:ID TAG RED |
| SC28P-1YELLOW | 制造商:Thomas & Betts 功能描述:ID TAG YELLOW |
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