參數(shù)資料
型號: SC28L92A1BS,557
廠商: NXP Semiconductors
文件頁數(shù): 40/73頁
文件大?。?/td> 0K
描述: IC UART DUAL W/FIFO 44PQFP
標(biāo)準(zhǔn)包裝: 2,450
系列: IMPACT
特點(diǎn): 故障啟動位檢測
通道數(shù): 2,DUART
FIFO's: 16 字節(jié)
電源電壓: 3.3V,5V
帶自動流量控制功能:
帶故障啟動位檢測功能:
帶調(diào)制解調(diào)器控制功能:
帶CMOS:
安裝類型: 表面貼裝
封裝/外殼: 48-VFQFN 裸露焊盤
供應(yīng)商設(shè)備封裝: 48-HVQFN EP(6x6)
包裝: 托盤
其它名稱: 935281063557
SC28L92A1BS
SC28L92A1BS-ND
45
2552K–AVR–04/11
ATmega329/3290/649/6490
ADC is used. To reduce power consumption in Power-down mode, the user can avoid the three
conditions above to ensure that the reference is turned off before entering Power-down mode.
10.8
Watchdog Timer
The Watchdog Timer is clocked from a separate On-chip Oscillator which runs at 1 MHz. This is
the typical value at V
CC = 5V. See characterization data for typical values at other VCC levels. By
controlling the Watchdog Timer prescaler, the Watchdog Reset interval can be adjusted as
shown in Table 10-2 on page 46. The WDR – Watchdog Reset – instruction resets the Watch-
dog Timer. The Watchdog Timer is also reset when it is disabled and when a Chip Reset occurs.
Eight different clock cycle periods can be selected to determine the reset period. If the reset
period expires without another Watchdog Reset, the ATmega329/3290/649/6490 resets and
executes from the Reset Vector. For timing details on the Watchdog Reset, refer to Table 10-2
To prevent unintentional disabling of the Watchdog or unintentional change of time-out period,
two different safety levels are selected by the fuse WDTON as shown in Table 10-1. Refer to
details.
Figure 10-7. Watchdog Timer
Table 10-1.
WDT Configuration as a Function of the Fuse Settings of WDTON
WDTON
Safety
Level
WDT Initial
State
How to Disable the
WDT
How to Change
Time-out
Unprogrammed
1
Disabled
Timed sequence
Programmed
2
Enabled
Always enabled
Timed sequence
WATCHDOG
OSCILLATOR
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