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參數(shù)資料
| 型號： | SC515849 |
| 廠商： | Motorola, Inc. |
| 英文描述： | Pressure Transducer, Series 19 mm, Compensated, Pressure Range: 0 psi to 100 psi, Gage, 7/16 UNF, 10 Vdc excitation |
| 中文描述： | MC9S12DT128設備的用戶手冊V02.09 |
| 文件頁數(shù)： | 3/138頁 |
| 文件大?。?/td> | 2083K |
| 代理商： | SC515849 |
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MC9S12DT128 Device User Guide — V02.09
3
V02.02
08 Mar
2002
08 Mar
2002
Changed XCLKS to PE7 in Table 2-2
Updated device part numbers in Figure 2-1
Updated BDM clock in Figure 3-1
Removed SIM description in overview & n
UPOSC
spec in Table A-15
Updated electrical spec of VDD & VDDPLL (Table A-4), IOL/IOH
(Table A-6), C
INS
(Table A-9), C
IN
(Table A-6 & A-15),
Updated interrupt pulse timing variables in Table A-6
Updated device part numbers in Figure 2-1
Added document numbers on cover page and Table 0-2
Cleaned up Fig. 1-1, 2-1
Updated Section 1.5 descriptions
Corrected PE assignment in Table 2-2, Fig. 2-5,6,7.
Corrected NVM sizes in Sections 16, 17
Added I
REF
spec for 1ATD in Table A-8
Added Blank Check in A.3.1.5 and Table A-11
Updated CRG spec in Table A-15
Added:
Pull-up columns to signal table,
Example for PLL Filter calculation,
Thermal values for junction to board and package,
BGND pin pull-up
Part Order Information
Global Register Table
Chip Configuration Summary
Device specific info on CRG
Modified:
Reduced Wait and Run IDD values
Mode of Operation chapter
Changed leakage current for ADC inputs down to +-1uA
Minor modification of PLL frequency/ voltage gain values
Corrected:
Pin names/functions on 80 pin packages
Interrupt vector table enable register inconsistencies
PCB layout for 80QFP VREGEN position
Corrected:
Register address mismatches in 1.5.1
Removed document order no. from Revision History pages
Renamed "Preface" section to "Derivative Differences and
Document references". Added details for derivatives missing
CAN0/1/4, BDLC, IIC and/or Byteflight
Added 2L40K mask set in section 1.6
Added OSC User Guide in Preface, “Document References”
Added oscillator clock connection to BDM in S12_CORE in fig 3-1
Corrected several register and bit names in “Local Enable” column
of Table 5.1 Interrupt Vector Locations
Section HCS12 Core Block Description: mentioned alternate clock
of BDM to be equivalent to oscillator clock
Added new section: “Oscillator (OSC) Block Description”
Corrected in footnote of Table "PLL Characteristics": fOSC = 4MHz
V02.03
14 Mar
2002
14 Mar
2002
V02.04
16 Aug
2002
16 Aug
2002
V02.05
12 Sep
2002
12 Sep
2002
V02.06
06 Nov
2002
06 Nov
2002
Version
Number
Revision
Date
Effective
Date
Author
Description of Changes
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