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參數(shù)資料
| 型號(hào)： | SC80C52XXX-36/883 |
| 廠商： | TEMIC SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 36 MHz, MICROCONTROLLER, CDIP40 |
| 封裝： | SIDE BRAZED, 40 PIN |
| 文件頁(yè)數(shù)： | 19/109頁(yè) |
| 文件大?。?/td> | 10824K |
| 代理商： | SC80C52XXX-36/883 |
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22
AT32UC3A
A local bus interface is provided for connecting the CPU to device-specific high-speed systems,
such as floating-point units and fast GPIO ports. This local bus has to be enabled by writing the
LOCEN bit in the CPUCR system register. The local bus is able to transfer data between the
CPU and the local bus slave in a single clock cycle. The local bus has a dedicated memory
range allocated to it, and data transfers are performed using regular load and store instructions.
Details on which devices that are mapped into the local bus space is given in the device-specific
“Peripherals” chapter of this data sheet.
Figure 9-1 on page 22 displays the contents of AVR32UC.
Figure 9-1.
Overview of the AVR32UC CPU
9.2.1
Pipeline Overview
AVR32 UC is a pipelined processor with three pipeline stages. There are three pipeline stages,
Instruction Fetch (IF), Instruction Decode (ID) and Instruction Execute (EX). The EX stage is
split into three parallel subsections, one arithmetic/logic (ALU) section, one multiply (MUL) sec-
tion and one load/store (LS) section.
Instructions are issued and complete in order. Certain operations require several clock cycles to
complete, and in this case, the instruction resides in the ID and EX stages for the required num-
ber of clock cycles. Since there is only three pipeline stages, no internal data forwarding is
required, and no data dependencies can arise in the pipeline.
Figure 9-2 on page 23 shows an overview of the AVR32 UC pipeline stages.
AVR32UC CPU pipeline
Instruction memory controller
High
Speed
Bus
master
MPU
Hi
gh
S
peed
Bus
Hi
gh
S
peed
Bus
OCD
system
O
CD
int
er
face
In
te
rr
up
tc
ont
ro
lle
ri
nte
rfa
ce
High
Speed
Bus slave
Hi
gh
S
peed
Bus
Data
R
A
M
in
te
rfa
ce
High Speed Bus master
Power/
Reset
control
R
ese
tint
erface
CPU Local
Bus
master
C
PU
Lo
ca
lBus
Data memory controller
32058K
AVR32-01/12
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| SC80C32XXX-36SV | 8-BIT, 36 MHz, MICROCONTROLLER, CDIP40 |
| SJ80C32XXX-12SV | 8-BIT, 12 MHz, MICROCONTROLLER, CQCC44 |
| S80C52EXXX-20SHXXX:D | 8-BIT, MROM, 20 MHz, MICROCONTROLLER, PQCC44 |
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