參數(shù)資料
型號(hào)： SC83C451CGA68
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O
中文描述： 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC68
封裝： PEDESTAL, PLASTIC, MO-047AE, SOT-188-3, LCC-68
文件頁(yè)數(shù)： 11/22頁(yè)
文件大?。?/td> 162K
代理商： SC83C451CGA68
Philips Semiconductors
Product specification
80C451/83C451/87C451
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
1998 May 01
11
AC ELECTRICAL CHARACTERISTICS
1
T
amb
= 0
°
C to +70
°
C, V
CC
= 5V
±
10%, V
SS
= 0V (87C451, 83C451, 80C451)
2
12MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
1/t
CLCL
Oscillator frequency:
Speed Versions
SC8XC451
SC8XC451
C
G
3.5
3.5
12
16
MHz
MHz
t
LHLL
2
ALE pulse width
127
2t
CLCL
–40
ns
t
AVLL
2
Address valid to ALE low
28
t
CLCL
–55
ns
t
LLAX
2
Address hold after ALE low
48
t
CLCL
–35
ns
t
LLIV
2
ALE low to valid instruction in
234
4t
CLCL
–100
ns
t
LLPL
2
ALE low to PSEN low
43
t
CLCL
–40
ns
t
PLPH
2
PSEN pulse width
205
3t
CLCL
–45
ns
t
PLIV
2
PSEN low to valid instruction in
145
3t
CLCL
–105
ns
t
PXIX
2
Input instruction hold after PSEN
0
0
ns
t
PXIZ
2
Input instruction float after PSEN
59
t
CLCL
–25
ns
t
AVIV
2
Address to valid instruction in
312
5t
CLCL
–105
ns
t
PLAZ
2
PSEN low to address float
10
10
ns
Data Memory
t
RLRH
3, 4
RD pulse width
400
6t
CLCL
–100
ns
t
WLWH
3, 4
WR pulse width
400
6t
CLCL
–100
ns
t
RLDV
3, 4
RD low to valid data in
252
5t
CLCL
–165
ns
t
RHDX
3, 4
Data hold after RD
0
0
ns
t
RHDZ
3, 4
Data float after RD
97
2t
CLCL
–70
ns
t
LLDV
3, 4
ALE low to valid data in
517
8t
CLCL
–150
ns
t
AVDV
3, 4
Address to valid data in
585
9t
CLCL
–165
ns
t
LLWL
3, 4
ALE low to RD or WR low
200
300
3t
CLCL
–50
3t
CLCL
+50
ns
t
AVWL
3, 4
Address valid to WR low or RD low
203
4t
CLCL
–130
ns
t
QVWX
3, 4
Data valid to WR transition
23
t
CLCL
–60
ns
t
WHQX
3, 4
Data hold after WR
33
t
CLCL
–50
ns
t
RLAZ
3, 4
RD low to address float
0
0
ns
t
WHLH
3, 4
RD or WR high to ALE high
43
123
t
CLCL
–40
t
CLCL
+40
ns
Shift Register
t
XLXL
5
Serial port clock cycle time
1.0
12t
CLCL
μ
s
t
QVXH
5
Output data setup to clock rising edge
700
10t
CLCL
–133
ns
t
XHQX
5
Output data hold after clock rising edge
50
2t
CLCL
–117
ns
t
XHDX
5
Input data hold after clock rising edge
0
0
ns
t
XHDV
NOTES: SEE NEXT PAGE
5
Clock rising edge to input data valid
700
10t
CLCL
–133
ns
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