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參數(shù)資料
| 型號： | SC83C451CGA68 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 80C51 8-bit microcontroller family 4K/128 OTP/ROM/ROMless, expanded I/O |
| 中文描述： | 8-BIT, MROM, 16 MHz, MICROCONTROLLER, PQCC68 |
| 封裝： | PEDESTAL, PLASTIC, MO-047AE, SOT-188-3, LCC-68 |
| 文件頁數(shù)： | 12/22頁 |
| 文件大?。?/td> | 162K |
| 代理商： | SC83C451CGA68 |
Philips Semiconductors
Product specification
80C451/83C451/87C451
80C51 8-bit microcontroller family
4K/128 OTP/ROM/ROMless, expanded I/O
1998 May 01
12
AC ELECTRICAL CHARACTERISTICS
1
(continued)
T
amb
= 0
°
C to +70
°
C, V
CC
= 5V
±
10%, V
SS
= 0V (87C451, 83C451, 80C451)
2
12MHz CLOCK
VARIABLE CLOCK
SYMBOL
FIGURE
PARAMETER
MIN
MAX
MIN
MAX
UNIT
Port 6 input (input rise and fall times = 5ns)
t
FLFH
8
PE width
270
3t
CLCL
+20
ns
t
ILIH
8
IDS width
270
3t
CLCL
+20
ns
t
DVIH
8
Data setup to IDS high or PE high
0
0
ns
t
IHDX
8
Data hold after IDS high or PE high
30
30
ns
t
IVFV
9
IDS to BFLAG (IBF) delay
130
130
ns
Port 6 output
t
OLOH
6
ODS width
270
3t
CLCL
+20
ns
t
FVDV
7
SEL to data out delay
85
85
ns
t
OLDV
6
ODS to data out delay
80
80
ns
t
OHDZ
6
ODS to data float delay
35
35
ns
t
OVFV
6
ODS to AFLAG (OBF) delay
100
100
ns
t
FLDV
6
PE to data out delay
120
120
ns
t
OHFH
7
ODS to AFLAG (SEL) delay
100
100
ns
External Clock
t
CHCX
10
High time
20
20
ns
t
CLCX
10
Low time
20
20
ns
t
CLCH
10
Rise time
20
20
ns
t
CHCL
10
Fall time
20
20
ns
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
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