參數(shù)資料
型號： SC87C51AGF40
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： CMOS single-chip 8-bit microcontrollers
中文描述： 8-BIT, UVPROM, 16 MHz, MICROCONTROLLER, CDIP40
文件頁數(shù)： 14/30頁
文件大?。?/td> 411K
代理商： SC87C51AGF40
Philips Semiconductors
Product specification
80C31/80C51/87C51
CMOS single-chip 8-bit microcontrollers
1996 Aug 16
14
AC ELECTRICAL CHARACTERISTICS FOR PHILIPS DEVICES
T
amb
= 0
°
C to +70
°
C, V
CC
= 5V
±
20%, V
SS
= 0V (PCB80C31/51, PCF80C31/51)
1, 2, 4, 5
VARIABLE CLOCK
3
SYMBOL
FIGURE
PARAMETER
MIN
MAX
UNIT
1/t
CLCL
Oscillator frequency:
Speed Versions
PCB8031/51
PCA/PCB/PCF80C31/51
PCB/PCF80C31/51
PCB/FB80C31/51
–2
–3
–4
–5
0.5
1.2
1.2
1.2
12
16
24
33
MHz
MHz
MHz
MHz
t
LHLL
1
ALE pulse width
2t
CLCL
–40
ns
t
AVLL
1
Address valid to ALE low
t
CLCL
–25
ns
t
LLAX
1
Address hold after ALE low
t
CLCL
–25
ns
t
LLIV
1
ALE low to valid instruction in
4t
CLCL
–65
ns
t
LLPL
1
ALE low to PSEN low
t
CLCL
–25
ns
t
PLPH
1
PSEN pulse width
3t
CLCL
–45
ns
t
PLIV
1
PSEN low to valid instruction in
3t
CLCL
–60
ns
t
PXIX
1
Input instruction hold after PSEN
0
ns
t
PXIZ
1
Input instruction float after PSEN
t
CLCL
–25
ns
t
AVIV
1
Address to valid instruction in
5t
CLCL
–80
ns
t
PLAZ
1
PSEN low to address float
10
ns
Data Memory
t
RLRH
2, 3
RD pulse width
6t
CLCL
–100
ns
t
WLWH
2, 3
WR pulse width
6t
CLCL
–100
ns
t
RLDV
2, 3
RD low to valid data in
5t
CLCL
–90
ns
t
RHDX
2, 3
Data hold after RD
0
ns
t
RHDZ
2, 3
Data float after RD
2t
CLCL
–28
ns
t
LLDV
2, 3
ALE low to valid data in
8t
CLCL
–150
ns
t
AVDV
2, 3
Address to valid data in
9t
CLCL
–165
ns
t
LLWL
2, 3
ALE low to RD or WR low
3t
CLCL
–50
3t
CLCL
+50
ns
t
AVWL
2, 3
Address valid to WR low or RD low
4t
CLCL
–75
ns
t
QVWX
2, 3
Data valid to WR transition
t
CLCL
–30
ns
t
WHQX
2, 3
Data hold after WR
t
CLCL
–25
ns
t
RLAZ
2, 3
RD low to address float
0
ns
t
WHLH
2, 3
RD or WR high to ALE high
t
CLCL
–25
t
CLCL
+25
ns
External Clock
t
CHCX
5
High time
15
ns
t
CLCX
5
Low time
15
ns
t
CLCH
5
Rise time
20
ns
t
CHCL
NOTES:
1. Parameters are valid over operating temperature range unless otherwise specified.
2. Load capacitance for port 0, ALE, and PSEN = 100pF, load capacitance for all other outputs = 80pF.
3. For all Philips speed versions only.
4. Interfacing the 80C31/51 to devices with float times up to 30ns is permitted. This limited bus contention will not cause damage to port 0
drivers.
5. V
CC
= 5V
±
10% for 33MHz.
5
Fall time
20
ns
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