參數(shù)資料
型號: SCAN15MB200TSQ
廠商: NATIONAL SEMICONDUCTOR CORP
元件分類: 通用總線功能
英文描述: Dual 1.5 Gbps 2:1/1:2 LVDS Mux/Buffer with Pre-Emphasis and IEEE 1149.6
中文描述: DUAL LINE TRANSCEIVER, PQCC48
封裝: LLP-48
文件頁數(shù): 7/12頁
文件大小: 599K
代理商: SCAN15MB200TSQ
Electrical Characteristics
(Continued)
Over recommended operating supply and temperature ranges unless other specified.
Symbol
Parameter
Conditions
Min
Typ
(Note 9)
Max
Units
LVDS OUTPUT DC SPECIFICATIONS
(SOA_n
±
, SOB_n
±
, LO_n
±
)
V
OD
Differential Output Voltage,
0% Pre-emphasis (Note 10)
V
OD
Change in V
OD
between
Complementary States
V
OS
Offset Voltage (Note 11)
V
OS
Change in V
OS
between
Complementary States
I
OS
Output Short Circuit Current
C
OUT2
Output Capacitance
R
L
is the internal 100
between OUT+
and OUT
250
360
500
mV
-35
35
mV
1.05
1.22
1.475
V
-35
35
mV
OUT+ or OUT Short to GND
OUT+ or OUT to GND when
TRI-STATE
21
-40
mA
4.0
pF
SUPPLY CURRENT (Static)
I
CC
Supply Current
All inputs and outputs enabled and
active, terminated with differential load
of 100
between OUT+ and OUT-.
ENA_0 = ENB_0 = ENL_0= ENA_1 =
ENB_1 = ENL_1 = L
225
275
mA
I
CCZ
Supply Current - Powerdown
Mode
SWITCHING CHARACTERISTICS—LVDS OUTPUTS
t
LHT
Differential Low to High Transition
Time
t
HLT
Differential High to Low Transition
Time
t
PLHD
Differential Low to High
Propagation Delay
t
PHLD
Differential High to Low
Propagation Delay
t
SKD1
Pulse Skew
t
SKCC
Output Channel to Channel Skew
0.6
4.0
mA
Use an alternating 1 and 0 pattern at
200 Mb/s, measure between 20% and
80% of V
OD
. (Note 16)
170
250
ps
170
250
ps
Use an alternating 1 and 0 pattern at
200 Mb/s, measure at 50% V
OD
between input to output.
1.0
2.5
ns
1.0
2.5
ns
|t
PLHD
–t
PHLD
| (Note 16)
Difference in propagation delay (t
PLHD
or t
PHLD
) among all output channels.
(Note 16)
RJ - Alternating 1 and 0 at 750MHz
(Note 13)
DJ - K28.5 Pattern, 1.5 Gbps (Note 14)
TJ - PRBS 2
7
-1 Pattern, 1.5 Gbps (Note
15)
Time from ENA_n, ENB_n, or ENL_n to
OUT
±
change from TRI-STATE to
active.
Time from ENA_n, ENB_n, or ENL_n to
OUT
±
change from Powerdown to
active
Time from ENA_n, ENB_n, or ENL_n to
OUT
±
change from active to
TRI-STATE or powerdown.
25
75
ps
50
115
ps
t
JIT
Jitter (0% Pre-emphasis)
(Note 12)
1.1
1.5
psrms
20
14
34
28
psp-p
psp-p
t
ON
LVDS Output Enable Time
0.5
1.5
μs
t
ON2
LVDS Output Enable time from
powerdown mode
10
20
μs
t
OFF
LVDS Output Disable Time
12
ns
S
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