參數(shù)資料
型號(hào)： SCC2691
廠商： NXP Semiconductors N.V.
英文描述： Universal asynchronous receiver/transmitter (DUART）(通用異步接收器/傳送器)
中文描述： 通用異步接收器/發(fā)送器（杜阿爾特）（通用異步接收器/傳送器）
文件頁(yè)數(shù)： 6/24頁(yè)
文件大小： 168K
代理商： SCC2691
Philips Semiconductors
Product specification
SCC2691
Universal asynchronous receiver/transmitter (UART)
1998 Sep 04
6
AC ELECTRICAL CHARACTERISTICS
1, 2, 3, 4
SYMBOL
PARAMETER
LIMITS
Typ
UNIT
Min
Max
Reset timing (Figure 3)
t
RES
Bus timing (Figure 4)
5
t
AS
t
AH
t
CS
t
CH
t
RW
t
DD
t
DF
t
DS
t
DH
t
RWD
MPI and MPO timing (Figure 5)
5
t
PS
MPI input setup time before RDN low
t
PH
MI input hold time after RDN low
t
PD
MPO output valid after WRN high
Interrupt timing (Figure 6)
t
IR
INTRN negated
Read RHR (RxRDY/FFULL interrupt)
Write THR (TxRDY, TxEMT interrupt)
Reset command (break change interrupt)
Reset command (MPI change interrupt)
Stop C/T command (counter interrupt)
Write IMR (clear of interrupt mask bit)
Clock timing (Figure 7)
t
CLK
X1/CLK high or low time
f
CLK9
X1/CLK frequency
t
CTC
Counter/timer clock high or low time
f
CTC8
Counter/timer clock frequency
t
RX
RxC high or low time
f
RX8
RxC frequency (16X)
RxC frequency (1X)
t
TX
TxC high or low time
f
TX8
TxC frequency (1X)
Transmitter timing (Figure 8)
t
TXD
TxD output delay from TxC external clock input on IP pin
t
TCS
Output delay from TxC low at OP pin to TxD data output
Receiver timing (Figure 9)
t
RXS
RxD data setup time before RxC high at external clock input on IP pin
t
RXH
RxD data hold time after RxC high at external clock input on IP pin
NOTES:
1. Parameters are valid over specified temp. range. See Ordering Information table for applicable operating temp. and V
CC
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all input signals swing between 0V and 3.0V with a transition time of
20ns max. For X1/CLK, this swing is between 0.4V and 4.0V. All time measurements are referenced at input voltages of 0.8V and 2V and
output voltages of 0.8V and 2V as appropriate.
3. Typical values are at +25
°
C, typical supply voltages, and typical processing parameters.
4. Test condition for outputs: C
L
= 150pF, except interrupt outputs. Test conditions for interrupt outputs: C
L
= 50pF, R
L
= 2.7k
to V
CC
.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. In this
case, all timing specifications apply referenced to the falling and rising edges of CEN. CEN and RDN (also CEN and WRN) are ORed inter-
nally. As a consequence, this signal asserted last initiates the cycle and the signal negated first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, this parameter defines the minimum high time between one CEN and the next. The RDN signal must
be negated for t
guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three rising edges of the X1 clock between writes.
8. These parameters are guaranteed by design, but are not 100% tested in production.
9. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
Reset pulse width
100
ns
A0–A2 setup time to RDN, WRN low
A0–A2 hold time from RDN, WRN low
CEN setup time to RDN, WRN low
CEN hold time from RDN, WRN high
WRN, RDN pulse width
Data valid after RDN low
Data bus floating after RDN high
Data setup time before WRN high
Data hold time after WRN high
Time between reads and/or writes
6, 7
10
100
0
0
150
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
125
110
50
30
150
30
30
ns
ns
ns
370
370
370
370
370
370
270
ns
ns
ns
ns
ns
ns
100
0
100
0
220
0
0
220
0
0
ns
MHz
ns
MHz
ns
MHz
MHz
ns
MHz
MHz
4.0
4.0
3.6864
2.0
1.0
TxC frequency (16X)
2.0
1.0
350
150
ns
ns
0
100
100
ns
ns
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