參數(shù)資料
型號(hào)： SCC2698BE1A84,512
廠商： NXP Semiconductors
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 0K
描述： IC UART OCTAL ENHANCED 84-PLCC
標(biāo)準(zhǔn)包裝： 15
特點(diǎn)： 故障啟動(dòng)位檢測(cè)
通道數(shù)： 8
FIFO's： 3 位
電源電壓： 5V
帶自動(dòng)流量控制功能： 是
帶故障啟動(dòng)位檢測(cè)功能： 是
帶調(diào)制解調(diào)器控制功能： 是
帶CMOS： 是
安裝類型： 表面貼裝
封裝/外殼： 84-LCC（J 形引線）
供應(yīng)商設(shè)備封裝： 84-PLCC
包裝： 管件
其它名稱： 935056380512
SCC2698BE1A84
SCC2698BE1A84-ND
Philips Semiconductors
Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
19
DC ELECTRICAL CHARACTERISTICS1, 2, 3 TA = 0 to +70_, VCC = 5.0 V " 10%, –40 to 85_C
SYMBOL
PARAMETER
TEST CONDITIONS
LIMITS
UNIT
SYMBOL
PARAMETER
TEST CONDITIONS
Min
Typ
Max
UNIT
VIL
Input low voltage
0.8
V
VIH
Input high voltage (except X1/CLK)
2.0
V
VIH
Input high voltage (X1/CLK)
0.8VCC
V
VOL
VOH
Output Low voltage
Output High voltage (except OD outputs)
IOL = 2.4mA
IOH = –400A
IOH = –100A
0.8VCC
0.9VCC
0.4
V
IIL
IIH
Input current Low, MPI and MPP pins
Input current High, MPI and MPP pins
VIN = 0
VIN = VCC
–50
20
A
II
Input leakage current
VIN = 0 to VCC
–10
10
A
IILX1
IIHX1
X1/CLK input Low current
X1/CLK input High current
VIN = GND, X2 = open
VIN = VCC, X2 = open
–100
100
A
IOZH
IOZL
Output off current High, 3-State data bus
Output off current Low, 3-State data bus
VIN = VCC
VIN = 0
–10
10
A
IODL
IODH
Open-drain output Low current in off state: IRQN
VIN = VCC
VIN = 0
–10
10
A
ICC
Power supply current
Operating mode
30
mA
ICC
Power down mode9
2.0
mA
NOTES:
1. Parameters are valid over specified temperature range. See ordering information table for applicable temperature range and operating
supply range.
2. All voltage measurements are referenced to ground (GND). For testing, all inputs swing between 0.4V and 2.4V with a transition time of 20ns
maximum. For X1/CLK this swing is between 0.4V and 4.4V. All time measurements are referenced at input voltages of VIL and VIH, as
appropriate.
3. Typical values are at +25
°C, typical supply voltages, and typical processing parameters.
4. Test condition for interrupt and MPP outputs: CL = 50pF, RL = 2.7k to VCC. Test conditions for rest of outputs: CL = 150pF.
5. Timing is illustrated and referenced to the WRN and RDN inputs. The device may also be operated with CEN as the ‘strobing’ input. CEN
and RDN (also CEN and WRN) are ANDed internally. As a consequence, the signal asserted last initiates the cycle and the signal negated
first terminates the cycle.
6. If CEN is used as the ‘strobing’ input, the parameter defines the minimum high times between one CEN and the next. The RDN signal must
be negated for tRWD guarantee that any status register changes are valid.
7. Consecutive write operations to the command register require at least three edges of the X1 clock between writes.
8. This value is not tested, but is guaranteed by design.
9. See UART applications note for power down currents less than 5
A.
10. Operation to 0MHz is assured by design. Minimum test frequency is 2MHz.
11. Address is latched on leading edge of read or write cycle.
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