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參數(shù)資料
| 型號： | SCC2698BE1A84,512 |
| 廠商： | NXP Semiconductors |
| 文件頁數(shù)： | 27/29頁 |
| 文件大小： | 0K |
| 描述： | IC UART OCTAL ENHANCED 84-PLCC |
| 標準包裝： | 15 |
| 特點： | 故障啟動位檢測 |
| 通道數(shù)： | 8 |
| FIFO's： | 3 位 |
| 電源電壓： | 5V |
| 帶自動流量控制功能： | 是 |
| 帶故障啟動位檢測功能： | 是 |
| 帶調(diào)制解調(diào)器控制功能： | 是 |
| 帶CMOS： | 是 |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 84-LCC（J 形引線） |
| 供應商設備封裝： | 84-PLCC |
| 包裝： | 管件 |
| 其它名稱： | 935056380512 SCC2698BE1A84 SCC2698BE1A84-ND |
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Philips Semiconductors
Product data sheet
SCC2698B
Enhanced octal universal asynchronous
receiver/transmitter (Octal UART)
2006 Aug 07
7
clock is used instead of a crystal, X1 must be driven and X2 left
floating as shown in Figure 9. The clock serves as the basic timing
reference for the baud rate generator (BRG), the counter/timer, and
other internal circuits. A clock frequency, within the limits specified in
the electrical specifications, must be supplied even if the internal
BRG is not used.
Table 1.
Register Addressing
Units A and B
Units E and F
A5
A4
A3
A2
A1
A0
READ (RDN=0)
WRITE
(WRN=0)
A5
A4
A3
A2
A1
A0
READ (RDN=0)
WRITE
(WRN=0)
0
MR1a, MR2a
1
0
MR1e, MR2e
0
1
SRa
CSRa
1
0
1
SRe
CSRe
0
1
0
BRG Test2
CRa
1
0
1
0
Reserved1
CRe
0
1
RHRa
THRa
1
0
1
RHRe
THRe
0
1
0
IPCRA
ACRA
1
0
1
0
IPCRC
ACRC
0
1
0
1
ISRA
IMRA
1
0
1
0
1
ISRC
IMRC
0
1
0
CTUA
CTPUA
1
0
1
0
CTUC
CTPUC
0
1
CTLA
CTPLA
1
0
1
CTLC
CTPLC
0
1
0
MR1b, MR2b
1
0
1
0
MR1f, MR2f
0
1
0
1
SRb
CSRb
1
0
1
0
1
SRf
CSRf
0
1
0
1
0
1X/16X Test2
CRb
1
0
1
0
1
0
Reserved1
CRf
0
1
0
1
RHRb
THRb
1
0
1
0
1
RHRf
THRf
0
1
0
Reserved1
1
0
1
0
Reserved1
0
1
0
1
Input port A
OPCRA
1
0
1
0
1
Input port C
OPCRC
0
1
0
Start C/T A
Reserved1
1
0
1
0
Start C/T C
Reserved1
0
1
Stop C/T A
Reserved1
1
0
1
Stop C/T C
Reserved1
Units C and D
Units G and H
0
1
0
MR1c, MR2c
1
0
MR1g, MR2g
0
1
0
1
SRc
CSRc
1
0
1
SRg
CSRg
0
1
0
1
0
Reserved1
CRc
1
0
1
0
Reserved1
CRg
0
1
0
1
RHRc
THRc
1
0
1
RHRg
THRg
0
1
0
1
0
IPCRB
ACRB
1
0
1
0
IPCRD
ACRD
0
1
0
1
0
1
ISRB
IMRB
1
0
1
0
1
ISRD
IMRD
0
1
0
1
0
CTUB
CTPUB
1
0
1
0
CTUD
CTPUD
0
1
0
1
CTLB
CTPLB
1
0
1
CTLD
CTPLD
0
1
0
MR1d, MR2d
1
0
MR1h, MR2h
0
1
0
1
SRd
CSRd
1
0
1
SRh
CSRh
0
1
0
1
0
Reserved1
CRd
1
0
1
0
Reserved1
CRh
0
1
0
1
RHRd
THRd
1
0
1
RHRh
THRh
0
1
0
Reserved1
1
0
Reserved1
0
1
0
1
Input port B
OPCRB
1
0
1
Input port D
OPCRD
0
1
0
Start C/T B
Reserved1
1
0
Start C/T D
Reserved1
0
1
Stop C/T B
Reserved1
1
Stop C/T D
Reserved1
NOTE:
1. Reserved registers should never be read during normal operation since they are reserved for internal diagnostics.
ACR = Auxiliary control register
SR
= Status Register
CR
= Command register
THR
= Tx holding register
CSR = Clock select register
RHR = Rx holding register
CTL
= Counter/timer lower
IPCR = Input port change register
CTPL = Counter/timer preset lower register
ISR
= Interrupt status register
CTU
= Counter/timer upper
IMR
= Interrupt mask register
CTPU = Counter/timer preset upper register
OPCR = Output port configuration register
MR
= Mode register
2. See Table 5 for BRG Test frequencies in this data sheet, and
“Extended baud rates for SCN2681, SCN68681, SCC2691, SCC2692, SCC68681
and SCC2698B” Philips Semiconductors ICs for Data Communications, IC-19, 1994.
BRG
The baud rate generator operates from the oscillator or external
clock input and is capable of generating 26 commonly used data
communications baud rates ranging from 50 to 115.2K baud.
Thirteen of these are available simultaneously for use by the
receiver and transmitter. Eight are fixed, and one of two sets of five
can be selected by programming ACR[7]. The clock outputs from
the BRG are at 16X the actual baud rate. The counter/timer can be
used as a timer to produce a 16X clock for any other baud rate by
counting down the crystal clock or an external clock. The clock
selectors allow the independent selection, by the receiver and
transmitter, of any of these baud rates or an external timing signal.
Counter–Timer
The four Counter/Timers are programmable 16 bit dividers that are
used for generating miscellaneous clocks or generating timeout
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