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SCF5250 Data Sheet: Technical Data, Rev. 1.3
28
Freescale Semiconductor
Figure 5 and Table 23 provide the timing diagram and timing parameters for the Debug AC.
Figure 5. Debug AC Timing Definition Diagram
H1
HIZ to High Impedance
鈥�
tbd
ns
H2
HIZ to Low Impedance
鈥�
tbd
ns
1 AC timing specs assume 40pF load capacitance on BCLK and a 50pF load capacitance on output pins. If this value is different,
the input and output timing specifications would need to be adjusted to match the clock load.
2 Outputs (8mA): DATA[31:16], ADDR[25,23:9]
3 Outputs (4mA): SDRAS, SDCAS, SDWE, SD_CS0, SDUDQM, SDLDQM, BCLKE
4 High Impedance (Three-State): DATA[31:16]
Table 23. Debug AC Timing Specification1
1 AC timing specs assume 50pF load capacitance on PSTCLK and output pins. If this value is different, the input and
output timing specifications would need to be adjusted to match the clock load.
Num
Characteristic
Min
Max
Units
D1
PSTCLK to signal Valid (Output valid)
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6
ns
D2
PSTCLK to signal Invalid (Output hold)
1.8
鈥�
ns
D32
2 DSCLK and DSI are internally synchronized. This setup time must be met only if recognition on a particular clock is
required.
Signal Valid to PSTCLK (Input setup)
3
鈥�
ns
D4
PSTCLK to signal Invalid (Input hold)
5
鈥�
ns
Table 22. Output AC Timing Specification (continued)
Num
Characteristic1
Min
Max
Units
PSTCLK
DSCLK
DSI
PST[3:0]
DDATA[3:0]
DSO
D3
D1
D2
D3
D4
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