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鍙冩暩(sh霉)璩囨枡
| 鍨嬭櫉锛� | SCF5250CAG120 |
| 寤犲晢锛� | Freescale Semiconductor |
| 鏂囦欢闋佹暩(sh霉)锛� | 56/56闋� |
| 鏂囦欢澶�?銆�?/td> | 0K |
| 鎻忚堪锛� | IC MPU COLDFIRE 120MHZ 144-QFP |
| 妯欐簴鍖呰锛� | 60 |
| 绯诲垪锛� | SCF52xx |
| 鏍稿績铏曠悊鍣細 | Coldfire V2 |
| 鑺珨灏哄锛� | 32-浣� |
| 閫熷害锛� | 120MHz |
| 閫ｉ€氭€э細 | EBI/EMI锛孖²C锛孖DE锛孧MC锛孲PI锛孶ART/USART |
| 澶栧湇瑷倷锛� | DMA锛孖²S锛孭OR锛屼覆琛岄煶闋�锛學DT |
| 杓稿叆/杓稿嚭鏁�(sh霉)锛� | 57 |
| 绋嬪簭瀛樺劜鍣ㄩ鍨嬶細 | ROMless |
| RAM 瀹归噺锛� | 128K x 8 |
| 闆诲 - 闆绘簮 (Vcc/Vdd)锛� | 1.08 V ~ 1.32 V |
| 鏁�(sh霉)鎿�(j霉)杞夋彌鍣細 | A/D 6x12b |
| 鎸暕鍣ㄥ瀷锛� | 鍏ч儴 |
| 宸ヤ綔婧害锛� | -40°C ~ 85°C |
| 灏佽/澶栨锛� | 144-LQFP |
| 鍖呰锛� | 鎵樼洡 |
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SCF5250 Data Sheet: Technical Data, Rev. 1.3
Freescale Semiconductor
9
Table 2. SCF5250 Signal Index
Signal Name
Mnemonic
Function
Input/
Output
Reset
State
Address
A[24:1]
A[23]/GPO54
24 address lines, address line 23
multiplexed with GPO54 and address 24
is multiplexed with A20 (SDRAM access
only).
Out
X
Read-write control
R/W
Bus write enable - indicates if read or
write cycle in progress
Out
H
Output enable
OE
Output enable for asynchronous
memories connected to chip selects
Out
negated
Data
D[31:16]
Data bus used to transfer word data
In/Out
Hi-Z
Synchronous row address
strobe
SDRAS/GPIO59
Row address strobe for external SDRAM.
Out
negated
Synchronous column
address strobe
SDCAS/GPIO39
Column address strobe for external
SDRAM
Out
negated
SDRAM write enable
SDWE/GPIO38
Write enable for external SDRAM
Out
negated
SDRAM upper byte
enable
SDUDQM/GPO53
Indicates during write cycle if high byte is
written
Out
鈥�
SDRAM lower byte enable SDLDQM/GPO52
Indicates during write cycle if low byte is
written
Out
鈥�
SDRAM chip selects
SD_CS0/GPIO60
SDRAM chip select
In/Out negated
SDRAM clock enable
BCLKE/GPIO63
SDRAM clock enable
Out
鈥�
System clock
BCLK/GPIO40
SDRAM clock output
In/Out
鈥�
ISA bus read strobe
IDE-DIOR/GPIO31
(CS2)
There is 1 ISA bus read strobe and 1 ISA
bus write strobe. They allow connection
of one independent ISA bus peripherals,
e.g. an IDE slave device.
In/Out
鈥�
ISA bus write strobe
IDE-DIOW/GPIO32
(CS2)
In/Out
鈥�
ISA bus wait signal
IDE-IORDY/GPIO33
ISA bus wait line - available for both
busses
In/Out
鈥�
Chip Selects[2:0]
CS0/CS4
CS1/QSPI_CS3/GPIO28
Enables peripherals at programmed
addresses.
CS[0] provides boot ROM selection
Out
In/Out
negated
Buffer enable 1
BUFENB1/GPIO29
Two programmable buffer enables allow
seamless steering of external buffers to
split data and address bus in sections.
In/Out
鈥�
Buffer enable 2
BUFENB2/GPIO30
In/Out
鈥�
Transfer acknowledge
TA/GPIO12
Transfer Acknowledge signal
In/Out
鈥�
Wake Up
WAKE_UP/GPIO21
Wake-up signal input
In
鈥�
Serial Clock Line
SCL0/SDATA1_BS1/GPIO41
SCL1/TXD1/GPIO10
Clock signal for Dual I2C module
operation
In/Out
鈥�
Serial Data Line
SDA0/SDATA3/GPIO42
SDA1/RXD1/GPIO44
Serial data port for second I2C module
operation
In/Out
鈥�
Receive Data
SDA1/RXD1/GPIO44
RXD0/GPIO46
Signal is receive serial data input for
DUART
In
鈥�
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